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datasheet single chip pc audio system codec+ stereo speaker amplifier+capless hp+ldo 92HD87 idt confidential 1 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 description the 92HD87 single-chip audio system is a low power optimized, high fidelity, 4-channel audio codec with integrated speaker amplifier, capless headphone amplifier, and low drop out voltage regulator. the high integration of the 92HD87 and the 40qfn package enables the smallest pcb footprint with the lowest system bom count and cost. the 92HD87 provides high qua lity hd audio capability to notebook and business desktop pc applications. features ? 4 channels (2 stereo dacs and 2 stereo adcs) with 24-bit resolution ? supports full-duplex stereo audio and simultaneous voip ? 2w/channel stereo speaker amplifier @ 4 ohms and 4.75v ? two headphone amplifiers ? one capless and one non-capless retaskable ? internal ldo for digital core supply ? +5 v analog power supply option ? dedicated btl high pass filter for speaker protection (ra re vision only) ? full hda015-b low power support ? audio inactivity transitions codec from d0 to d3 low power mode ? resume from d3 to d0 with audio activity in < 10 msec ? d3 to d0 transition with < -65db pop/click ? port presence detect in d3 with or without bit clock ? optional analog pc beep in d3 ? additional vendor specific modes for even lower power ? microsoft wlp premium logo compliant, as defined in wlp 3.9 ? support for 1.5v and 3.3v hda signaling ? digital microphone inputs (mono or stereo) ? aux audio mode (see orderable part numbers for support) ? high performance analog mixer ? 2 adjustable vref out pins for analog microphone bias ? 5 analog ports with port presence detect + stereo speaker differential output) ? analog and digital pc beep support ? 40-pad qfn rohs package
idt confidential 2 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo software support ? intuitive idt hd sound graphical user interfac e that allows configur ability and preference set- tings ? 12 band fully parametric equalizer ? constant, system-level effects tuned to optimize a particular platform can be combined with user-mode ?presets? tailored for specific acoustical environments and applications ? system-level effects automatically disabled when external audio connections made ? dynamics processing ? enables improved voice articulation ? compressor/limiter allows higher average volu me level without resonances or damage to speakers. ? idt vista apo wrapper ? enables multiple apos to be used with the idt driver ? microphone beam forming, acoustic ec ho cancellation, and noise suppression ? dynamic stream switching ? improved multi-streaming user experience with less support calls ? broad 3 rd party branded software includi ng creative, dolby, dts, and srs
idt confidential 3 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo table of contents 1. description ................................................................................................................ ........ 10 1.1. overview ................................................................................................................. .........................10 1.2. orderable part numbers ................................................................................................... ...............10 2. detailed description ..................................................................................................... 11 2.1. port functionality ............ ...................................................................... ............ ......... ......................11 2.1.1. port characteristics ............................. ...................................................................... .........11 2.1.2. vref_out ............................................................................................................... ..............12 2.1.3. jack detect ............................................................................................................ ............12 2.2. analog mixer ............................................................................................................. .......................13 2.3. adc multiplexers ................................... ...................................................................... ....................13 2.4. power management ...... ......................................................................................... .......... ................13 2.5. afg d0 ................................................................................................................... .........................14 2.6. afg d1 ................................................................................................................... .........................14 2.7. afg d2 ................................................................................................................... .........................14 2.8. afg d3 ................................................................................................................... .........................14 2.8.1. afg d3cold ............................................................................................................. ..........15 2.9. vendor specific function group po wer states d4/d5 ......... .................................................. .........15 2.10. low-voltage hda signaling ............................................................................................... ............15 2.11. multi-channel captur e ............... .................................................................................... .................16 2.12. digital microphone support .............................................................................................. .............18 2.13. analog pc-beep .......................................................................................................... ..................22 2.14. digital pc-beep ......................................................................................................... ....................22 2.15. headphone drivers ............. .............................................................................. ............ .................22 2.16. eapd .................................................................................................................... .........................23 2.17. btl amplifier ........................................................................................................... ......................26 2.18. btl amplifier high-pass filter .......................................................................................... .............26 2.18.1. filter description .................................................................................................... ..........26 2.19. gpio .................................................................................................................... ..........................27 2.19.1. gpio pin mapping and shared functions .........................................................................27 2.19.2. digital microphone/gpio selection .................................................................................27 2.20. hd audio hda015-b support ............................................................................................... .........27 2.21. digital core voltage regulator .......................................................................................... ............28 2.22. aux audio support ....................................................................................................... ..................28 2.22.1. general conditions in aux audio mode: ...........................................................................28 2.22.2. ?playback path? port behavior ................ ......................................................................... 29 2.22.3. when port e presence detect = 0 ....................................................................................29 2.22.4. when port e presence detect = 1 ....................................................................................29 2.22.5. system diagrams ......................................................................................................3 1 2.22.6. eapd .................................................................................................................. .............32 2.22.7. analog pc_beep ........................................................................................................ .....32 2.22.8. f irmware/software requirements: ............... ....................................................................32 3. characteristics ............................................................................................................ ... 33 3.1. electrical specifications ......................... ....................................................................... ...................33 3.1.1. absolute maximum ratings ............................................................................................... 33 3.1.2. recommended operating conditions ................................................................................33 3.2. 92HD87 analog performance characteristics ........ ........................................................................ .34 3.3. ac timing specs .......................................................................................................... ...................38 3.3.1. hd audio bus timing ............................. ....................................................................... .....38 3.3.2. digital microphone timing ........................ ...................................................................... ...39 3.3.3. class-ab btl amplifier performance ...............................................................................39 3.3.4. capless headphone supply characteristics .. ........................................................ ............39 4. functional block diagrams ....................................................................................... 40 5. widget information and supported command verbs ....................................... 41 6. port configurations ..................................................................................................... 42 6.1. pin configuration default register settings ... ........................................................................... .......43 7. widget information ........................................................................................................ 4 4 7.1. widget list .............................................................................................................. .........................44
idt confidential 4 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8. widgets .................................................................................................................... ............ 46 8.1. reset key ................................................................................................................ ........................46 8.2. root (nid = 00h): vendorid ............................................................................................... .............46 8.2.1. root (nid = 00h): revid ................................................................................................ ....47 8.2.2. root (nid = 00h): nodeinfo ...................... ....................................................................... ..47 8.3. afg (nid = 01h): nodeinfo .. .................................................................................... .......... .............48 8.3.1. afg (nid = 01h): fgtype ................................................................................................ .48 8.3.2. afg (nid = 01h): afgcap ................................................................................................ 49 8.3.3. afg (nid = 01h): pcmcap ...............................................................................................5 0 8.3.4. afg (nid = 01h): streamcap ............................................................................................5 1 8.3.5. afg (nid = 01h): inampcap .............................................................................................5 2 8.3.6. afg (nid = 01h): pwrstatecap .........................................................................................53 8.3.7. afg (nid = 01h): gpiocnt ............................................................................................... 54 8.3.8. afg (nid = 01h): outampcap ...................... ....................................................................54 8.3.9. afg (nid = 01h): pwrstate .............................................................................................. .55 8.3.10. afg (nid = 01h): unsolresp ...................... ....................................................................56 8.3.11. afg (nid = 01h): gpio ................................................................................................. ..56 8.3.12. afg (nid = 01h): gpioen ............................................................................................... 57 8.3.13. afg (nid = 01h): gpiodir .............................................................................................. 58 8.3.14. afg (nid = 01h): gpiowakeen .....................................................................................58 8.3.15. afg (nid = 01h): gpiounsol ..........................................................................................59 8.3.16. afg (nid = 01h): gpiosti cky ............. ................................................................... .........59 8.3.17. afg (nid = 01h): subid ................................................................................................ ..60 8.3.18. afg (nid = 01h): gpioplrty ............................................................................................ 61 8.3.19. afg (nid = 01h): gpiodrive ...........................................................................................6 1 8.3.20. afg (nid = 01h): dmic ................................................................................................. ...62 8.3.21. afg (nid = 01h): dacmode ...........................................................................................63 8.3.22. afg (nid = 01h): adcmode ...........................................................................................64 8.3.23. afg (nid = 01h): eapd ..... ............................................................................................ .64 8.3.24. afg (nid = 01h): portuse .............................................................................................. .66 8.3.25. afg (nid = 01h): vspwrstate ............. ................................................................... .........67 8.3.26. afg (nid = 01h): anaport .............................................................................................. .68 8.3.27. afg (nid = 01h): anabeep .............................................................................................6 9 8.3.28. afg (nid = 01h): anabtl ............................................................................................... 69 8.3.29. afg (nid = 01h): anacapless .........................................................................................72 8.3.30. afg (nid = 01h): reset ................................................................................................ ...75 8.3.31. afg (nid = 01h): auxaudio ............................................................................................. 75 8.4. porta (nid = 0ah): wcap .................................................................................................. ..............76 8.4.1. porta (nid = 0ah): pincap ....................... ....................................................................... ..77 8.4.2. porta (nid = 0ah): conlst .............................................................................................. ...78 8.4.3. porta (nid = 0ah): conlstentry0 ............... .......................................................................79 8.4.4. porta (nid = 0ah): inampleft ........................................................................................... .79 8.4.5. porta (nid = 0ah): inampright .........................................................................................8 0 8.4.6. porta (nid = 0ah): conselectctrl ............... .......................................................................8 0 8.4.7. porta (nid = 0ah): pwrstate ............................................................................................ .81 8.4.8. porta (nid = 0ah): pinwcntrl ........................................................................................... .81 8.4.9. porta (nid = 0ah): unsolresp ................... .......................................................................8 2 8.4.10. porta (nid = 0ah): chsense ...........................................................................................8 3 8.4.11. porta (nid = 0ah): eapdbtll r .............. ............................ ............ ...................... .........83 8.4.12. porta (nid = 0ah): configdefault ............. .......................................................................84 8.5. portb (nid = 0bh): wcap .................................................................................................. ..............86 8.5.1. portb (nid = 0bh): pincap ....................... ....................................................................... ..88 8.5.2. portb (nid = 0bh): conlst .............................................................................................. ...89 8.5.3. portb (nid = 0bh): conlstentry0 ............... .......................................................................90 8.5.4. portb (nid = 0bh): conselectctrl ............... .......................................................................9 0 8.5.5. portb (nid = 0bh): pwrstate ............................................................................................ .90 8.5.6. portb (nid = 0bh): pinwcntrl ........................................................................................... .91 8.5.7. portb (nid = 0bh): unsolresp ................... .......................................................................9 2 8.5.8. portb (nid = 0bh): chsense ............................................................................................. 92
idt confidential 5 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.5.9. portb (nid = 0bh): eapdbtll r .............. ................................................................ .........93 8.5.10. portb (nid = 0bh): configdefault ............. .......................................................................93 8.6. portc (nid = 0ch): wcap .................................................................................................. .............96 8.6.1. portc (nid = 0ch): pincap ......................... ..................................................................... ..97 8.6.2. portc (nid = 0ch): conlst .............................................................................................. ..98 8.6.3. portc (nid = 0ch): conlstentry0 ......................................................................................99 8.6.4. portc (nid = 0ch): inampleft ........................................................................................... 99 8.6.5. portc (nid = 0ch): inampright .................. .....................................................................100 8.6.6. portc (nid = 0ch): conselectctrl .............. .....................................................................100 8.6.7. portc (nid = 0ch): pwrstate ...........................................................................................1 01 8.6.8. portc (nid = 0ch): pinwcntrl .........................................................................................10 1 8.6.9. portc (nid = 0ch): unsolresp ................... .....................................................................102 8.6.10. portc (nid = 0ch): chsense .........................................................................................103 8.6.11. portc (nid = 0ch): eapdbtllr ...................................................................................103 8.6.12. portc (nid = 0ch): configdefault ............. .....................................................................104 8.7. portd (nid = 0dh): wcap .................................................................................................. ...........106 8.7.1. portd (nid = 0dh): pincap ......................... ..................................................................... 108 8.7.2. portd (nid = 0dh): conlst .............................................................................................. 109 8.7.3. portd (nid = 0dh): conlstentry0 ....................................................................................110 8.7.4. portd (nid = 0dh): conselectctrl .............. .....................................................................110 8.7.5. portd (nid = 0dh): pwrstate ...........................................................................................1 10 8.7.6. portd (nid = 0dh): pinwcntrl .........................................................................................11 1 8.7.7. portd (nid = 0dh): eapdbtllr .............. ................................................................ .......112 8.7.8. portd (nid = 0dh): configdefault ............... .....................................................................112 8.8. vendor reserved (nid = 0eh) ............ ...................................................................... ............ .........115 8.9. portf (nid = 0fh): wcap .................................................................................................. ............115 8.9.1. portf (nid = 0fh): pincap .............................................................................................. .116 8.9.2. portf (nid = 0fh): conlst ..................... ......................................................................... .117 8.9.3. portf (nid = 0fh): conlstentry0 .....................................................................................118 8.9.4. portf (nid = 0fh): inampleft ..........................................................................................1 18 8.9.5. portf (nid = 0fh): inampright ................... .....................................................................11 9 8.9.6. portf (nid = 0fh): conselectctrl ............... .....................................................................119 8.9.7. portf (nid = 0fh): pwrstate ..................... ....................................................................... 120 8.9.8. portf (nid = 0fh): pinwcntrl ................... .......................................................................1 20 8.9.9. portf (nid = 0fh): unsolresp .................... .....................................................................12 1 8.9.10. portf (nid = 0fh): chsense ..........................................................................................12 2 8.9.11. portf (nid = 0fh): eapdbtllr .............. ............................ ............ ...................... .......122 8.9.12. portf (nid = 0fh): configdefault ...................................................................................123 8.10. vendor reserved (nid = 10h) ............. ...................................................................... .......... ........125 8.11. dmic0 (nid = 11h): wcap ................................................................................................. ..........125 8.11.1. dmic0 (nid = 11h): pincap ...........................................................................................12 7 8.11.2. dmic0 (nid = 11h): inampleft .......................................................................................128 8.11.3. dmic0 (nid = 11h): inampright ....................................................................................128 8.11.4. dmic0 (nid = 11h): pwrstate .........................................................................................12 9 8.11.5. dmic0 (nid = 11h): pinwcntrl .......................................................................................130 8.11.6. dmic0 (nid = 11h): unsolresp ......................................................................................130 8.11.7. dmic0 (nid = 11h): chsense ........................................................................................131 8.11.8. dmic0 (nid = 11h): configdefault .................................................................................131 8.12. reserved (nid = 12h) .................................................................................................... ..............134 8.13. dac0 (nid = 13h): wcap .................................................................................................. ..........134 8.13.1. dac0 (nid = 13h): cnvtr ............................................................................................... 135 8.13.2. dac0 (nid = 13h): procst ate (ra revision only) ...........................................................136 8.13.3. dac0 (nid = 13h): outampleft ................... ..................................................................137 8.13.4. dac0 (nid = 13h): outampright ................ ..................................................................137 8.13.5. dac0 (nid = 13h): pwrstate .................... .....................................................................138 8.13.6. dac0 (nid = 13h): cnvtrid ............................................................................................1 39 8.13.7. dac0 (nid = 13h) : eapdbtllr ............ ................................................................ .......139 8.13.8. dac0 (nid = 13h): procindex (ra revision only) ..........................................................140 8.14. dac1 (nid = 14h): wcap .................................................................................................. ..........140
idt confidential 6 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.14.1. dac1 (nid = 14h): cnvtr ............................................................................................... 142 8.14.2. dac1 (nid = 14h): procst ate (ra revision only) ...........................................................143 8.14.3. dac1 (nid = 14h): outampleft ................... ..................................................................144 8.14.4. dac1 (nid = 14h): outampright ................ ..................................................................144 8.14.5. dac1 (nid = 14h): pwrstate .................... .....................................................................144 8.14.6. dac1 (nid = 14h): cnvtrid ............................................................................................1 45 8.14.7. dac1 (nid = 14h) : eapdbtllr ............ ................................................................ .......146 8.14.8. dac1 (nid = 14h): procindex (ra revision only) ..........................................................146 8.15. dac2 (nid = 22h): wcap .................................................................................................. ..........147 8.15.1. dac2 (nid = 22h): cnvtr ............................................................................................... 149 8.15.2. dac2 (nid = 22h): outampleft ................... ..................................................................150 8.15.3. dac2 (nid = 22h): outampright ................ ..................................................................150 8.15.4. dac2 (nid = 22h): pwrstate .................... .....................................................................151 8.15.5. dac2 (nid = 22h): cnvtrid ............................................................................................1 52 8.15.6. dac2 (nid = 22h) : eapdbtllr ............ ................................................................ .......152 8.16. adc0 (nid = 15h): wcap .................................................................................................. ..........153 8.16.1. adc0 (nid = 15h): conlst ............................................................................................15 4 8.16.2. adc0 (nid = 15h): conlstentry0 ..................................................................................155 8.16.3. adc0 (nid = 15h): cnvtr ............................................................................................... 155 8.16.4. adc0 (nid = 15h): procstate ........................................................................................156 8.16.5. adc0 (nid = 15h): pwrstate .................... .....................................................................157 8.16.6. adc0 (nid = 15h): cnvtrid ............................................................................................1 58 8.17. adc1 (nid = 16h): wcap .................................................................................................. ..........158 8.17.1. adc1 (nid = 16h): conlst ............................................................................................16 0 8.17.2. adc1 (nid = 16h): conlstentry0 ..................................................................................160 8.17.3. adc1 (nid = 16h): cnvtr ............................................................................................... 161 8.17.4. adc1 (nid = 16h): procstate ........................................................................................162 8.17.5. adc1 (nid = 16h): pwrstate .................... .....................................................................163 8.17.6. adc1 (nid = 16h): cnvtrid ............................................................................................1 64 8.18. adc0mux (nid = 17h): wcap ............................................................................................... ......164 8.18.1. adc0mux (nid = 17h): conlst ......................................................................................166 8.18.2. adc0mux (nid = 17h): conlstentry4 ...........................................................................166 8.18.3. adc0mux (nid = 17h): conlstentry0 ...........................................................................167 8.18.4. adc0mux (nid = 17h): outampcap .............. ...............................................................167 8.18.5. adc0mux (nid = 17h): outampleft ............ ..................................................................168 8.18.6. adc0mux (nid = 17h): outampright ......... ..................................................................168 8.18.7. adc0mux (nid = 17h): conselectctrl ......... ..................................................................169 8.18.8. adc0mux (nid = 17h): pwrs tate ..................................................................................169 8.18.9. adc0mux (nid = 17h): eapd btllr ............. ........................................................ .......170 8.19. adc1mux (nid = 18h): wcap ............................................................................................... ......171 8.19.1. adc1mux (nid = 18h): conlst ......................................................................................172 8.19.2. adc1mux (nid = 18h): conlstentry4 ...........................................................................173 8.19.3. adc1mux (nid = 18h): conlstentry0 ...........................................................................173 8.19.4. adc1mux (nid = 18h): outampcap .............. ...............................................................174 8.19.5. adc1mux (nid = 18h): outampleft ............ ..................................................................175 8.19.6. adc1mux (nid = 18h): outampright ......... ..................................................................175 8.19.7. adc1mux (nid = 18h): conselectctrl ......... ..................................................................176 8.19.8. adc1mux (nid = 18h): pwrs tate ..................................................................................176 8.19.9. adc1mux (nid = 18h): eapd btllr ............. ........................................................ .......177 8.20. reserved (nid = 19h) .................................................................................................... . .............177 8.21. reserved (nid = 1ah) .............................. ...................................................................... .............177 8.22. mixer (nid = 1bh): wcap ................................................................................................. ...........177 8.22.1. mixer (nid = 1bh): inampcap .......................................................................................179 8.22.2. mixer (nid = 1bh): conlst ............................................................................................. 180 8.22.3. mixer (nid = 1bh): conlstentry4 ............. .....................................................................180 8.22.4. mixer (nid = 1bh): conlstentry0 ............. .....................................................................181 8.22.5. mixer (nid = 1bh): inampleft0 ......................................................................................181 8.22.6. mixer (nid = 1bh): inampright0 ...................................................................................182 8.22.7. mixer (nid = 1bh): inampleft1 ......................................................................................183
idt confidential 7 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.22.8. mixer (nid = 1bh): inampright1 ...................................................................................183 8.22.9. mixer (nid = 1bh): inampleft2 ......................................................................................184 8.22.10. mixer (nid = 1bh): inampright2 .................................................................................184 8.22.11. mixer (nid = 1bh): inampleft3 ............... .....................................................................185 8.22.12. mixer (nid = 1bh): inampright3 .................................................................................185 8.22.13. mixer (nid = 1bh): inampleft4 ............... .....................................................................186 8.22.14. mixer (nid = 1bh): inampright4 .................................................................................186 8.22.15. mixer (nid = 1bh): inampleft5 ............... .....................................................................187 8.22.16. mixer (nid = 1bh): inampright5 .................................................................................187 8.22.17. mixer (nid = 1bh): pwrstate ........................................................................................18 8 8.23. mixeroutvol (nid = 1ch): wcap ........................................................................................... ......188 8.23.1. mixeroutvol (nid = 1ch): conlst ..................................................................................190 8.23.2. mixeroutvol (nid = 1ch): conlstentry0 ..... ..................................................................190 8.23.3. mixeroutvol (nid = 1ch): outampcap .........................................................................191 8.23.4. mixeroutvol (nid = 1ch): outampleft ..........................................................................192 8.23.5. mixeroutvol (nid = 1ch): outampright .......................................................................192 8.23.6. mixeroutvol (nid = 1ch): pwrstate ......... .....................................................................193 8.24. reserved (nid = 1dh) .............................. ...................................................................... .............194 8.25. reserved (nid = 1eh) .............................. ...................................................................... .............194 8.26. reserved (nid = 1fh) .................................................................................................... ..............194 8.27. reserved (nid = 19h) .................................................................................................... ..............194 8.28. reserved (nid = 20h) .................................................................................................... ..............194 8.29. digbeep (nid = 21h): wcap .......................... ..................................................................... ........194 8.29.1. digbeep (nid = 21h): outampcap .............. ..................................................................195 8.29.2. digbeep (nid = 21h): outa mpleft ................................................................................195 8.29.3. digbeep (nid = 21h): pwrsta te .....................................................................................196 8.29.4. digbeep (nid = 21h): gen .............................................................................................1 97 9. pinout ..................................................................................................................... ............ 198 9.1. pin assignment ........................................................................................................... ...................198 9.2. pin table ................................................................................................................ ........................199 9.3. package outline and package dimensions .............. ........................................................ ............. 200 9.4. standard reflow profile data ............................................................................................. ...........201 10. disclaimer ................................................................................................................ ....... 202 11. document revision history .................................................................................... 203
idt confidential 8 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo list of figures figure 1. multi-channel capture ... ............................................................................................ .......................16 figure 2. multi-channel timing diagr am ............. ........................................................................... ..................17 figure 3. single digital microphone (data is ported to both left and right channels .. ............................ .........20 figure 4. stereo digital microphone configuration ............................................................................. ...........21 figure 5. hp eapd example to be replaced by single pin for internal amp ............. ............................ .........25 figure 6. aux mode block diagram ........................ ...................................................................... .................30 figure 7. hd audio bus timing ................................................................................................. .....................38 figure 8. functional block diagram ............................................................................................ ...................40 figure 9. widget diagram ...................................................................................................... ........................41 figure 10. port configurations ................................................................................................ .......................42 figure 11. pin assignment ..................................................................................................... ......................198 figure 12. 40qfn package diagram .............................................................................................. .............200 figure 13. solder reflow profile ....................... ....................................................................... ....................201
idt confidential 9 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo list of tables table 1. port functionality ................................................................................................... ..........................11 table 2. analog output port behavior ................. ......................................................................... .................12 table 3. power management ........... ................................................................... ............ ........... ....................13 table 4. example channel mapping ........................ ...................................................................... .................16 table 6. btl amp status ....................................................................................................... ........................24 table 7. headphone amp enable configuration ................................................................................... .........24 table 8. eapd low power behavior .............................................................................................. ...............24 table 9. eapd behavior ........................................................................................................ ........................25 table 10. aux mode table ...................................................................................................... .......................30 table 11. electrical specification: maximum ratings .......................................................................... .........33 table 12. recommended operating conditions .................................................................................... ........33 table 13. 92HD87 analog performance characteristics ... ........................................................................ ....34 table 14. hd audio bus timing ................................................................................................. ....................38 table 15. digital mic timing ............................ ...................................................................... ..........................39 table 16. class-ab btl amplifier perf ormance .................................................................................. ..........39 table 17. capless headphone supply ........................ .................................................................... ..............39 table 18. pin configuration default settings .......... ........................................................................ ...............43 table 19. command format for verb with 4-bit identifier ............. .................................... ............ .......... .......44 table 20. command format for verb with 12-bit identifi er ...................................................................... ......44 table 21. solicited response format ........................................................................................... .................44 table 22. unsolicited response format ......................................................................................... ...............44 table 23. high definition audio wi dget ........................................................................................ .................44 table 24. pinout list ......................................................................................................... ...........................199 table 25. standard reflow profile ...................................................................... ............ ........... ..................201
idt confidential 10 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 1. description 1.1. overview the 92HD87 is a high fidelity, 4-channel audio code c compatible with the in tel high definition (hd) audio interface. the 92HD87 codec provides high quality, hd audio capability to notebooks and business desktops. the 92HD87 is designed to meet or exceed premium logo requirements for microsoft?s windows logo program as indicated in wlp 3.09. the 92HD87 provides stereo 24-bit, full duplex resolu tion supporting sample rates up to 192khz by the dac and adc. the 92HD87 supports a wide range of notebook and business desktop 4-chan- nel configurations. an integrated btl stereo amplifie r is ideal for driving an integrated speaker in mobile, ultra-mobile, business or desktop computers. mic inputs can be programmed with 0/10/20/30db boost. for more advanced configurations, the 92HD87 has 2 general purpose i/o (gpio). the port presence detect capab ilities allow the codecs to detect when audio devices are connected to the codec. load impedance sensing helps identify attached peripherals for easy set-up and a bet- ter user experience. the fully parametric idt softeq can be initiated upon headphone jack insertion and removal for protection of notebook speakers. the 92HD87 operates with a 1.5v, 1.8v or 3.3v di gital supply and a 5v analog supply. it can also work with 1.5v and 3.3v hda signaling. the 92HD87 is available in a 40-pin qfn environmental (rohs) package. 1.2. orderable part numbers yy = silicon stepping/revision, contact sales for current data add an ?8? to the end for tape and reel delivery. min/mult order quantity 2.5ku. 92HD87b1x5ndgxyyx 4 channel, stereo btl, 40qfn, aux mode, 3.3v hda signaling 92HD87b1a5ndgxyyx customer specific part number 92HD87b2x5ndgxyyx 4 channel, stereo btl, 40qfn, no aux mode, 3.3v hda signaling 92HD87b3x5ndgxyyx 4 channel, stereo btl, 40qfn, aux mode, 1.5v hda signaling 92HD87b3a5ndgxyyx customer specific part number 92HD87b4x5ndgxyyx 4 channel, stereo btl, 40qfn, no aux mode, 1.5v hda signaling
idt confidential 11 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 2. detailed description 2.1. port functionality multi-function (input / output) ports allow for the highest possible flexibility. 3 or 4 bi-directional ports, 2 headphone ports, and a high power btl amplifier support a wide variety of consumer desktop and mobile system use models. for the codec the port ca pabilities are as follows ? port a supports ? headphone ? line out ? line input ? mic with 0/10/20/30 db boost and vref_out ? port b supports ? capless headphone out ? capless line out ? port c supports ? line out (not available on tb revision) ? line in ? mic with 0/10/20/30 db boost and vref_out ? port d supports ? btl (l+/l-) stereo out ? port f supports ? line out ? line in ? mic with 0/10/20/30 db boost 2.1.1. port characteristics universal (bi-directional) jacks are supported on ports c (input only on tb revision) and f. port a is birdirectional also. ports a and b are designed to drive 32 ohm (nominal) headphones or a 10k (nominal) load. line level outputs are intended to drive an external 10k load (nominal) and an on board shunt resistor of 20-47k (nominal). however, applications may support load impedances of 5k ohms and above. input ports are 50k (nominal) at the pin. dac full scale outputs and intended full scale input levels are 1v rms at 5v. line output ports and headphone output ports on the codec may be configured for +3dbv full scale output levels by using a vendor specific verb. pins port input output headphone btl mic bias (vref pin) input boost amp 24/23 a yes yes yes yes yes 27/26 b yes yes 15/16 c yes yes yes yes 35/36 d yes yes 13/14 f yes yes yes 3d m i c 0y e s y e s table 1. port functionality
idt confidential 12 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo output ports are always on to prevent pops/clicks associated with charging and discharging output coupling capacitors. this maintains proper bias on output coupling caps even in power state d3 as long as avdd is available. unused ports shou ld be left unconnected. when updating existing designs to use the codec, ensure that there are no conflicts between the output ports on the codec and existing circuitry. 2.1.2. vref_out ports c & a support vref_out pins for biasing el ectret cartridge microphones. settings of 80% avdd, 50% avdd, gnd, and hi-z are supported. a ttempting to program a pin widget control with a reserved or unsupported value will cause the asso ciated vref_out pin to assume a hi-z state and the pin widget control vref_en field will retu rn a value of ?000 ? (hi-z) when read. 2.1.3. jack detect plugs inserted to a jack on ports a, b, c are detected using sense_a. plugs inserted to a jack on ports f, dmic0, are detected using sense_b. per hda015-b, the detection circuit operates when the codec is in d0 - d3 and can also operate if both the codec and contro ller are in d3 (no bus clock.) jack detection requires that all supplies (analog and digital) are active and stable. when avdd is not present, the value report ed in the pin widget is invalid. when the hd audio bus is in a low power state (r eset asserted and cloc k stopped) the codec will generate a power state change request when a change in port connectivity is sensed and then generate an unsolicited response after the hd audio link has been brought out of a low power state and the device has been enum erated. per hda015-b, this will take less than 10ms. the following table summarizes the proper resistor tolerances for different analog supply voltages. see reference design for more information on jack detect implementation. afg power state input enable output enable port behavior d0-d2 1 1 not allowed. port is active as output. input path is mute. 1 0 active - port enabled as input 0 1 active - port enabled as output 0 0 inactive -port is powered on (low out put impedance) but drives silence only. d3 - 0 inactive (lower power) - port keeps out put coupling caps charged if port uses caps. - 1 low power state. if enabled, b eep will output from the port d3cold - - inactive (lower power) - port keeps output coupling caps charged if port uses caps. d4 - - inactive (lower power) - port keeps out put coupling caps charged if port uses caps. d5 - - off - charge on coupling caps (if used) will not be maintained. table 2. analog output port behavior avdd nominal voltage (+/- 5%) resistor tolerance pull-up resistor tolerance sense_a/b 4.75v 1% 1% resistor sense_a sense_b 39.2k port a (hp0) na 20.0k port b (hp1) port f 10.0k port c dmic0 5.11k 2.49k pull-up to avdd pull-up to avdd
idt confidential 13 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 2.2. analog mixer the mixer supports independent gain (-34.5 to +12db in 1.5db steps) on each input as well as inde- pendent mutes on each input. the following inputs are available: ?port a ?port c ?port f 2.3. adc multiplexers the codec implements 2 adc input multiplexers. these multiplexers incor porate the adc record gain function (0 to +22.5db gain in 1.5db steps) as an output amp and allow a preselection of one of 7 possible inputs: ?port a ?port c ?port f ? mixer output ?dmic 0 2.4. power management the hd audio specification defines power states, power state widgets, and power state verbs. power management is implemented at several leve ls. the audio function group (afg) , all con- verter widgets, and all pin complexes support the power state verb f05/705. converter widgets are active in d0 and inactive in d1-d3. the following table describes what function ality is active in each power state. function d0 d1 1 d2 d3 d3cold vendor specific d4 vendor specificd5 digital microphone inputs on off off off off off off dac on off off off off off off d2s on off off off off off off adc on off off off off off off adc volume control on off off off off off off ref adc on off off off off off off analog clocks on off off off off off off gpio pins on on on on 5 on on off vrefout pins on on off off off off off input boost on on off off off off off analog mixer on on off off off off off mixer volumes on on off off off off off analog pc_beep on on on on off off off digital pc_beep on on on on 5 off off off lo/hp amps on on on low drive 2 low drive 2 low drive 2 off capless hp amps on on on low drive 2 low drive 2 low drive 2 off btl amp on on on low drive 2 off off off vag amp ononon low drive 3 low drive low drive off table 3. power management
idt confidential 14 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo the d3-default state is available for hd audio compliance. the programmable values, exposed via vendor-specific settings, are under idt device driver control for further power reduction. the analog mixer, line and headphone amps, port presence detect, and internal references may be disabled using vendor specific verbs. use of t hese vendor specific verbs will cause pops. the default power state for the audio function group after reset is d3. 2.5. afg d0 the afg d0 state is the active state for the device. all functions are active if their power state (if they support power management at their node level) has been set to d0. 2.6. afg d1 d1 is a lower power mode where all converter wid gets are disabled. analog mixer and port functions are active. the part will resume from thed1 to thed0 state within 1 ms. 2.7. afg d2 the d2 state further reduces power by disabling t he mixer and port function s. the port amplifiers and internal references remain active to keep port coupling caps charged and the system ready for a quick resume to either th e d1 or d0 state. the part will resume from the d2 stat e to the d0 state within 2ms. 2.8. afg d3 the d3-default state is available for hd audio compliance. all conver ters are shut down. port ampli- fiers and references are active but in a low power state to prevent pops. resume times may be lon- ger than those from d2, but still less than 10ms to meet intel low power goals. the default power state for the audio function group after power is applied is d3. the traditional use for d3 was as a transitional st ate before power was removed (d3 cold) before the system entered into standby, hibernate, or shut-down. to conserve power, intel now promotes using d3 whenever there are no active streams or other activi ty that requires the part to consume full power. the system remains in s0 during this time. when a stream request or user activity requires the codec to become active, the driver will immediately transition the codec from d3 to d0. to port sense on on on on 4 off off off reference bias generator on on on on on on off reference bandgap core on on on on on on off hd audio-link on on on on 5 limited off off 1. no dac or adc streams are active. analog mixing and loop thru are supported. 2. vag is kept active when ports are disabled or in d3/d3c old/d4. pc_beep is supported in d3 but may be attenuated and distorted depending on load impedance. 3. vag is always ramped up and down gradually, except in the case of a sudden power removal. vag is active in d2/d3 but in a low power state. 4. both avdd and dvdd must be available for port sense to operate. 5. not active if bitclk is not running (controller in d3), but can signal power state change request (pme) function d0 d1 1 d2 d3 d3cold vendor specific d4 vendor specificd5 table 3. power management
idt confidential 15 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo enable this use model, the codec must resume within 10ms and not pop. intel hda015-b / low power white paper power goals are < 30mw w hen analog pc_beep is not enabled, and < 60mw when analog pc_beep is enabled. (charge pump and btl amplifier power excluded.) while in afg d3, the hd audio controller may be in a d0 state (hd audio bus active) or in a d3 state (hd audio bus held in reset with no bit_clk, sdata_out, or sync activity.) the expected behav- ior is as follows (see the hda015- b section for more information): 2.8.1. afg d3cold the d3cold power state is the lowe st power state available that does not use vendor specific verbs. while in d3cold, the codec will still respond to bus requests to reve rt to a higher power state (dou- ble afg reset, link reset). however, audio processi ng, port presence detect, and other functions are disabled. per the hd audio bus hda015-b, the d3cold state is intended to be used just prior to removing power to the codec. ty pically, power will be removed wi thin 200ms. however, the codec may exit from the d3cold state by generating 2, back-to-back, afg reset events. resume time from d3cold is less than 200ms. 2.9. vendor specific functi on group power states d4/d5 the codec introduces vendor specific power states. a vendor defined verb is added to the audio function group that combines multiple vendor spec ific power control bits into logical power states for use by the audio driver. the 2 states defined of fer lower power than the 5 existing states defined in the hd audio specification and hda015-b. the vendor specific d4 state provides lower digital power consumption relative to d3co ld by disabling hd audio link responses. vendor specific d5 fur- ther reduces power consumption on the digital supply by turning off gpio drivers, and reduces ana- log power consumption by turning off all an alog circuitry except for reset circuits. states d4/d5 are not entered until d3cold has been requested. software can pre-program the d4 or d5 state as a re-definition of how the part will be have when the d3cold power state is requested or software may enter d3cold, then set the d4 or d5. the preferred method is to request d3cold, then select d4 or d5 as desired.this will reduce the severity of pops encounter ed when entering d4 or d5. both power states require a link re set or removal of dvdd to exit. the codec may pop when using these verbs and transi tion times to an active state (d1 or d0 for example) may take several seconds. 2.10. low-voltage hda signaling the codec is compatible with either 1.5v or 3. 3v hda bus signaling; the voltage selection is done dynamically based on the input voltage of dvdd_io. dvdd_io is currently not a logic configuration pin, but rather provides the digital power supply to be used for the hda bus signals. function hda bus active hda bus stopped port presence detect state change unsolicited response wake event 1 followed by an uns olicited response 1.the port presence detect circuit is currently d ependent on a clock and must be changed to gener- ate a wake event. gpio state change unsolicited response wake event followed by an unsolicited response
idt confidential 16 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo when in 1.5v mode, the codec can correctly decode bitclk, sync, reset# and sdo as they operate at 1.5v; additionally it will drive sdi and sdo at 1.5v. none of the gpios are affected, as they always function at their nominal voltage (dvdd or avdd). 2.11. multi-channel capture the capability to assign multiple ?adc converters? to the same st ream is supported to meet the microphone array requirements of vista and future operating systems. single converter streams are still supported this is done by assigning unique non zero stream ids to each converter. all capture devices (adcs 0 and 1) may be used to create a multi-channel input stream. there are no restric- tions regarding digital microphones. the adc converters can be associated with a single stream as long the sample rate and the bits per sample are the same. the assignment of converter to channel is done using the ?cnvtrid? widget and is restricted to even values. the adc conver ters will always put out a stereo sample and there- fore require 2 channels per converter. the stream will not be generated unle ss all entries for the targeted converters are set identically, and the total number of assigned converter channels ma tches the value in the nmbrchan field. these are listed the ?multi-converter stream critical entries.? table. an example of a 4 channel steam with adc0 supplying channels 0&1 and adc1 supplying chan- nels 2 & 3 is shown below. a 4 channel stream can be created by assigning the same non-zero stream id ?strm= n? to both adc0 and adc1. the sample rates must be se t the same and the num- ber of channels must be set to 4 channels ?nmbrchan = 0011?. figure 1. multi-channel capture the following figure describes the bus waveform for a 24-bit, 48khz capture stream with id set to 1. adc1 cnvtrid (nid = 0x08) [3:0] ch = 2 adc0 cnvtrid (nid = 0x07) [3:0] ch=0 table 4. example channel mapping stream id data length adc0 left channel adc0 right channel adc1 left channel adc1 right channel stream id data length adc1 left channel adc1 right channel adc0 left channel adc0 right channel adc0.cnvrtid.channel = 0 adc1.cnvrtid.channel = 2 adc0.cnvrtid.channel = 2 adc1.cnvrtid.channel = 0
idt confidential 17 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo figure 2. multi-channel timing diagram adc[1:0] cnvtr bit number sub field name description [15] strmtype stream type (type): 0: pcm 1: non-pcm (not supported) [14] frmtsmplrate sample base rate 0= 48khz 1=44.1khz [13:11] smplratemultp sample base rate multiple 000=48khz/44.1khz or less 001= x2 010= x3 (not supported) 011= x4 100-111= reserved [10:8] smplratediv sample base rate divisor 000= divide by 1 001= divide by 2 (not supported) 010= divide by 3 (not supported) 011= divide by 4 (not supported) 100= divide by 5 (not supported) 101= divide by 6 (not supported) 110= divide by 7 (not supported) 111= divide by 8 (not supported) table 5: mult-channel 0 0 0 sdi bitclk 1 0 0 1 1 0 0 stream id data length stream tag adc0 l23 adc0 l0 adc0 r23 adc0 r0 adc1 l23 adc1 l0 adc1 r23 adc1 r0 left left right right adc0 adc1 data block
idt confidential 18 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 2.12. digital microphone support the digital microphone interface permits connection of a digital microphone(s) to the codec via the dmic0, and dmic_clk 3-pin interface. the dmic0 signal is an input that carry individual channels of digital microphone data to the adc. in the ev ent that a single microphone is used, the data is ported to both adc channels. this mode is select ed using a vendor specific verb and the left time slot is copied to the adc left and right inputs. the dmic_clk output is controllable from 4.70 4mhz, 3.528mhz, 2.352mhz, 1.176mhz and is syn- chronous to the internal master cloc k. the default frequency is 2.352mhz. the dmic data input is reported as a stereo input pin widgets that incorporate a boost amplifier. the pin widgets are shown connected to the adcs thro ugh the same multiplexors as the analog ports. although the internal implementation is different between the analog ports and the digital micro- phones, the functionality is the same . in most cases, the default values for the dmic clock rate and data sample phase will be appropriate and an audio driver will be able to configure and use the digi- tal microphones exactly like an analog microphone. to conserve power, the analog portion of the ad c will be turned off if the d-mic input is selected. when switching from the digital microphone to an analog input to the adc, the analog portion of the adc will be brought back to a full power state and allowed to stabilize before switching from the dig- ital microphone to the analog input. this should take less than 10ms. dmic pin widgets support port presence detect directly using sense-b input. [6:4] bitspersmpl bits per sample 000= 8 bits (not supported) 001= 16 bits 010= 20 bits 011= 24 bits 100-111= reserved [3:0] nmbrchan number of channels number of channels for this stream in each ?sample block? of the ?packets? in each ?frame? on the link. 0000=1 channel (not supported) 0001 = 2 channels ? 1111= 16 channels. [7:4] strm software-programmable integer representing link stream id used by the converter widget. by conven- tion stream 0 is reserved as unused. [3:0] ch integer representing lowest channel used by con- verter. 0 and 2 are valid entries if assigned to the same stream, one adc must be assigned a value of 0 and the other adc assigned a value of 2. table 5: mult-channel
idt confidential 19 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo the codec supports the following digital microphone configurations: digital mics data sample adc conn. notes 0 n/a n/a no digital microphones 1 single edge 0, or 1 when using a microphone that supports multiplexed operation (2-mics can share a common data line), configure the microphone for ?left? and select mono operation using the vendor specific verb. ?left? d-mic data is used for adc left and right channels. 2 double edge on either dmic_0 or 1 0, or 1 external logic required to support sampling on a single digital mic pin channel on rising edge and second digital mic right channel on falling edge of dmic_clk for those digital microphones that don?t support alternative clock edge (multiplexed output) capability. power state dmic widget enabled? dmic_clk output dmic_0,1 notes d0 yes clock capable input capable dmic_clk output is enabled when either dmic_0 or input widget is enabled. otherwise, the dmic_clk remains low d1-d3 yes clock disabled input disabled dmic_clk is high-z with weak pull-down d0-d3 no clock disabled input disabled dmic_clk is high-z with weak pull-down d4 - clock disabled input disabled dmic_clk is high-z with weak pull-down d5 - clock disabled input disabled dmic_clk is high-z with weak pull-down
idt confidential 20 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo figure 3. single digital microphone (data is ported to both left and right channels dmic_0 or dmic_1 dmic_clk right channel left channel valid data valid data valid data dmic_0 or dmic_1 dmic_clk single line in pin on-chip multiplexer pin digital microphone on-chip off-chip mux stereo channels output stereo adc0 or 1 pcm dmic_0 or dmic_1 dmic_clk left & right channel valid data valid data valid data valid data single ?left? microphone, dmic input set to mono input mode. single microphone not supporting multiplexed output.
idt confidential 21 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo figure 4. stereo digital microphone configuration note: some digital microphone implementations support data on either edge, therefore, the external mux may not be required. dmic_0 or dmic_1 dmic_clk right channel left channel valid data r valid data l valid data r valid data l valid data r digital microphones dmic_clk mux stereo channels output pin pin external multiplexer on-chip multiplexer on-chip off-chip stereo adc0 or 1 pcm mux dmic_0 or dmic_1
idt confidential 22 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 2.13. analog pc-beep the codec does not support automatic routing of the pc_beep pin to all outputs when the hd-link is in reset. analog pc-beep may be supported during hd-link reset if analog pc_beep is manually enabled before entering reset and the level shifters are locked. analog pc_beep is mixed at the port and only ports enabled as outputs will pass pc_b eep. analog pc_beep (o r a digital equivalent) must not prevent passing wlp when analog pc_beep is enabled. analog pc_beep, when enabled, must not prevent ot her audio sources from playing (we must mix not mux.) an activity monitor will allow the btl amplifier (and cap-less headphone amp lifiers if possible) to remain in shutdown when the function group is in d3 until the beep pin is active and then quickly change to an active state (within 10ms) to pass the beep tone. beeps from ich (from beep.sys) can have a frequency of about 37hz to about 32khz. beep duration is prog rammable from 1ms to about 32 seconds. a typi- cal beep under windows xp is 500hz or 2khz and lasts 75ms or 150ms. due to external xor gates used as mixers, the idle state may be logic 0 or logic 1. pc-beep may be attenuated and distorted when the codec is in d3 depending on the load imped- ance seen by the output amplifier since all ports are in a low power state while in d3. load imped- ances of 10k or larger can supp ort full scale outputs but lower impedance loads will distort unless the output amplitude is reduced. analog pc_beep is not supported in d3 co ld, or the vendor specific states d4/d5. 2.14. digital pc-beep this block uses an 8-bit divider value to generate the pc beep from the 48khz hd audio sync pulse. the digital pc_beep block generates the beep tone on all pin complexes that are currently configured as outputs. the hd audio spec states that the beep tone frequency = (48khz hd audio sync rate) / (4*divider), producing tones from 47 hz to 12 khz (logarithmic scale). other audio sources are disabled when digital pc_beep is active. it should be noted that digital pc be ep is disabled if the divider = 00h. pc-beep may be attenuated and distorted when the codec is in d3 depending on the load imped- ance seen by the output amplifier since all ports are in a low power state while in d3. load imped- ances of 10k or larger can supp ort full scale outputs but lower impedance loads will distort unless the output amplitude is reduced. digital pc_beep requires a clock to operate and the codec will prevent the system from stopping the bus clock wh ile in d3 by setting the clock_stop_ok bit to 0 to indicate that the part requires a clock. 2.15. headphone drivers the codec implements capless headphone outputs. the microsoft windows logo program allows up to the equivalent of 100ohms in series. however, an output level of +3dbv at the pin is required to support 300mv at the jack with a 32ohm load and 1v with a 320 ohm load. microsoft allows device and system manufactures to limit output voltages to address eu safety requirements. (wlp 3.09 - please refer to the latest windows logo program requirements from microsoft.) the capless headphone drivers are supplied with +/-2.5v derived from avdd. therefore, it is possi- ble to run the headphone supply from 5v and maintain ~60mw peak output power into 32 ohm headphones. head phone performance will degrade if more than one po rt is driving a 32 ohm load.
idt confidential 23 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 2.16. eapd the eapd pin (pin 47) is a dedicated, bi-direction al control pin. although named external amplifier power down (eapd) by the hd audio specification, this pin operates as an external amplifier power up signal. the eapd value is reflected on the eapd pin; a 1 causes the external amp lifier to power up (equivalent to d0), and a 0 causes it to power down (equivalent to d3.) when the eapd value = 1, the eapd pin must be placed in a state appropriate to the current power state of the associated pin widget even though th e eapd value (in the regist er) may remain 1. the de fault state of this pin is 0 (driving low.) the pin defaults to an open-drain configuration (an external pull-up is recom- mended.) per the hd audio specification and hda015-b, multiple ports may control eapd. the eapd pin assumes the highest power state of all the eapd bits in all of the pin complexes. the default value of eapd is 1 (powered on), but t he fg power state will override and the pin will be low. a port will request external amp power up when its power stat e is active (fg and pin widget power state is d1 or d0) or (analog pc_beep is enabled and port is enabled as an output) a nd the port?s eapd bit is set to 1. the state of the eapd pi n (unless configured as an input or held low by an external circuit when configured as an open dr ain output) will be the logical or of the external amp power up requests from all ports. by default, the eapd pin al so functions as t he mute#/shutdown# input for the internal btl amplifier. in this mode, a low value at the pin (either due to internal eapd being 0, or to an external entity forc- ing the pin low) will cause the intern al btl amplifier to mute or en ter a low power state depending on the amplifier configur ation. (see below) vendor specific verbs are available to configure this pin. these verbs retain their values across link and single function group resets but are set to their default values by a power on reset: mode1 mode0 eapd pin function description 0 0 open drain i/o value at pin is wired-and of eapd bit and external signal. (default) 0 1 cmos output value of eapd bit in pin widget is forced at pin 1 0 cmos input external signal controls inte rnal amps. eapd bit in pin widget ignored 1 1 cmos input external signal controls inte rnal amps. eapd bit in pin widget ignored control flag description eapd pin mode 1:0 defines if eapd pin is used as input, outpu t, or bi-directional port (open drain) btl/hp sd 0 = amp cont rolled by eapd pin only (default) / 1 = amp controlled by power st ate (pin and fg) only btl/hp sd mode 0 = amp will mute when disabled. / 1 = amp will shut down (enter a low power state) when disabled (default) btl/hp sd inv 0 = amp will power down (or mute) when eapd pin is low (default) / 1 = amp will power down (or mute) when eapd pin is high.
idt confidential 24 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo btl sd btl sd mode btl sd inv eapd pin state amp state 0 0 0 0 amplifier is mute 0 0 0 1 amplifier is active 0 0 1 0 amplifier is active 0 0 1 1 amplifier is mute 0 1 0 0 amplifier is in a low power state (default 1 ) 1.eapd bit is set to one by default but the eapd state is 0 after power-on rese t because the function group is not in d0. the state after a single or double functi on group reset will be compliant with hda015-b. 0 1 0 1 amplifier is active 0 1 1 0 amplifier is active 0 1 1 1 amplifier is in a low power state 1 0 na na amplifier follows pin/function group power state and will mute when disabled 1 1 na na amplifier follows pin/function group power state and will enter a low power state when disabled table 6. btl amp status hp sd hp sd mode hp sd inv eapd pin state headphone amp state 0 0 0 0 amplifier is mute 0 0 0 1 amplifier is active 0 0 1 0 amplifier is active 0 0 1 1 amplifier is mute 0 1 0 0 amplifier is in a low power state (default 1 ) 1.eapd bit is set to one by default but the eapd state is 0 after po wer-on reset because the function group is not in d0. the state after a single or double function group reset will be compliant with hda015-b. 0 1 0 1 amplifier is active 0 1 1 0 amplifier is active 0 1 1 1 amplifier is in a low power state 1 0 na na amplifier follows pin/functi on group power state and will mute when disabled 1 1 na na amplifier follows pin/functi on group power state and will enter a low power state when disabled table 7. headphone amp enable configuration beep override eapd pin value 1 1. when pin is enabled as open drain or cmos output. description 0 forced to low when in d2 or d3 follows description in hd audio spec. external amplifier is shut down when pin or function group power state is d2 or d3 independent of value in eapd bit. 1 always follows eapd bit power state is ignored and eapd pin follows eapd bit value only to allow pc_beep support in d2 and d3 table 8. eapd low power behavior
idt confidential 25 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo figure 5. hp eapd example to be replaced by single pin for internal amp afg power state reset# beep override eapd power state pin behavior d0-d3 asserted (low) - - active low immedi ately after power on, otherwise the previous state is retained across fg and link reset events d0 de-asserted (high) - - active - pin reflects eapd bit unless held low by external source. d1 de-asserted (high) - d0-d1 active - pin refl ects eapd bit unless held low by external source. d2 de-asserted (high) disabled d0-d2 pin fo rced low to disable external amp d2 de-asserted (high) enabled d0-d2 active - pin re flects eapd bit unless held low by external source. d3 de-asserted (high) disabled d0-d3 pin fo rced low to disable external amp d3 de-asserted (high) enabled d0-d3 active - pin re flects eapd bit unless held low by external source. d3cold de-asserted (high) - - pin forced low to disable external amp d4 de-asserted (high) - - pin forced low to disable external amp d5 de-asserted (high) - - pin hi-z (off) table 9. eapd behavior mute + up/down buttons kbc codec spkr amp scan codes os a_sd a_eapd spkr_en# gpio_1 sync from audio gui to kbc sync from kbc to os (mute led on same board) hp audio control block diagram
idt confidential 26 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 2.17. btl amplifier an integrated class-ab stereo btl amplifier is provided to directly drive 4 ohm speaker (2w @ 4.75v) or 8 ohm speaker (1w @ 4.75v). no external filter is needed for cable runs of 18? or less. an internal dc blocking filter prevents distortion when the audio source has dc content, and prevents unintentional power consumption when pausing audio playback. the amplifier may be controlled using the eapd pin (see eapd section.) the btl amplifier includes thermal management circuitry. when the codec reaches a temperature of about 135 degrees, the output amplitude of the btl amp is gradually lowered until the tempera- ture falls below 135. maximum gain for the btl amplifier is programmab le. the following 4 gain se ttings relative to a nominal line output are desired: +6.5db, +9.5db, +14.5db and +16.5db. absolute gain may vary and the suggested accuracy is +/-1.5db. the gain is ex posed in a vendor specific widget and is intended to mimic the pin programmable gain implemented in discrete btl amplifiers commonly used in note- book computers. 2.18. btl amplifier high-pass filter not available on tb revision. for mobile applications, speakers are often in capable of reproducing low frequency audio and unable to handle the maximum output power of th e btl amplifier. a high-pass filter is implemented in the dac output path to reduce the amount of low frequency energy reaching speakers attached to the btl amplifier. this can prevent speaker failure. 2.18.1. filter description the high-pass filter is derived from the common biqu adratic filter and provides a 12db/octave roll-off. the filter may be programmed for a -3db response at: 100hz, 200hz, 300hz , 400hz, 500hz, 750hz, 1khz, or 2khz. the high pass filter is enabled by default with a cut-off frequency of 300hz. the filter may be bypassed us ing the associated verb (processing state verb). smu mute other external power amp sd# internal btl amp eapd pin control sd/mute codec vdd eapd sd/mute internal headphone amp
idt confidential 27 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo the filter is implemented in digital before the digital to analog converter. there are 2 major conse- quences to implementing the filter in the digital domain: 1. all ports connected to the dac will be affect ed by the high-pass filer when it is enabled. 2. analog paths (such as when the microphone input is routed through the mixer to the btl ampli- fier) are not affected. like the other analog inputs, pc_beep is not affected by the digital high-pass filter. to ensure that the speakers attached to the btl amplifier are not harmed by low frequency audio entering the pc_beep input, an external filter must be implemented. fortunately, it is common practice to imple- ment an attenuation circuit and dc blocking capacito r at the pc_beep input. this attenuator/filter is easily adjusted to restrict low frequency audio. the easiest approach is to reduce the value of the dc blocking capacitor but other approaches are equally effective. 2.19. gpio 2.19.1. gpio pin mapping and shared functions 2.19.2. digital microphone/gpio selection 2 functions are available on the dmic_clk/gpio1 (pin 2) and the dmic_0/gpio2 (pin 3) pins. to determine which function is enabled, the order of precedence is followed: 1. if gpios are not enabled through the afg, then at reset, pins 2 and 4 are pulled low by an inter- nal pull-down resistor. 2. if the gpio 1 is enabled, the 2 dmic pins become mute (unless programmed for gpio use) and pin 2 becomes an internal pull-down. 3. if gpio2 is enabled through the afg, pin 3 becomes a gpio and is pulled low by an internal pull-down resistor. 4. if the port is en abled as an input, the di gital microphones will be used. 5. if the port is not enabled as an input or if the pin is configured as a gpio, the digital microphone path will be mute. 2.20. hd audio hda015-b support although hda015-b is not yet co mplete (not a dcn), the 92HD87 will implemen t complete support for the specification building on the support alre ady present in previous products. hda015-b fea- tures supported are: ? persistence of many configuration options through bus and function group reset. ? the ability to support port presen ce detect in d3 even when the hd audio bus is in a low power state (no clock.) ? fast resume times from low power states: 1m s d1 to d0, 2ms d2 to d0, 10ms d3 to d0. ? notification if persistent register settings have been unexpectedly reset. gpio # pin supply gpi/o gpi gp o vrefout dmic vol pull up pull down 1 2 dvdd yes clk 50k 2 3 dvdd yes in 50k
idt confidential 28 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 2.21. digital core voltage regulator the digital core operates from 1.4 to 1.98v making it compatible with 1.5v (5%) and 1.8v (10%) sup- ply voltages. many systems require that the code c use a single 3.3v digital supply, so an inte- grated regulator is included on die. the regulator uses pin 7, dvdd, as its voltage source. the output of the ldo is connected to pin 1 and the di gital core. a 10uf capacitor must be placed on pin 1 for proper load regulat ion and regulator stability. the digital core voltage regulator is only dependent on dvdd. the codec digital logic and i/o (unless referenced to avdd) will operate in the absence of avdd. dvdd and avdd supply sequencing for the application of power and the re moval of power is neither defined nor guaranteed. it is common for desktop systems to supply avdd from the system standby supply and the codec will tolerate, indefinitely, the cond ition where avdd is active but dvdd and dvddio are inactive. to prevent pops, software is expected to mute pa ths as close to the port as is possible when chang- ing power states or signal topology. 2.22. aux audio support the codec supports an au xiliary audio mode where analog audio is supporte d by default after power is supplied with the hd audio bus disabled. in this mode, an analog input is routed to one of several output ports depending on jack presence detection. in addition to shutting off the codec btl and hea dphone amplifiers when the docked device output jack is used, the btl am plifier will be disabled when the he adphone jacks are used, and the head- phone amplifiers will be di sabled when not in use. 2.22.1. general conditions in aux audio mode: ? hd audio link is off (rst# is 0, active, and bitclk is 0, inac tive. codec does not need to mon- itor bitclk to enter/exit this mode but must not depend on bitclk to operate.) ? hd audio codec analog and digital supplies are active. ? port a may be an optional headphone jack (normal and aux audio mode) or an internal micro- phone port (normal mode only) ? port b connect to the system headphone jack. ? port c connects to the system microphone jack ? port d connects to the internal speakers. ? port e is not present on the codec but the port presence detect is available and used to con- trol internal resources. ? port f is connected to the dock au x audio in (it is an input port) ? eapd is used to control the pow er state of the mixer, btl amp lifier, and headp hone amplifiers. the amplifiers are off if eapd is held low. ? internal circuitry will delay enab ling (change power state, un-mut e, etc.) the output amplifiers after the application of power or eapd=1 to prevent pops. ? internal circuitry will orch estrate power down (eapd = 0) to prevent pops. ? eapd must be forced lo w before removing power. ? no special dock present signal needed. only port presence detect for port e is used to disable the speaker amplifier if the docked device ha s something plugged into its headphone jack. ? dcn hda015-b ?clock-less d3? operation presents a problem. clock stop ok or similar commu- nication will be used to prevent problems when an os driver a ttempts to put the hd audio bus controller into d3 to save power. the bus must not be place into reset with the clock stopped or
idt confidential 29 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo unless eapd is forced low or d3cold has been se t. the enable bit in th e aux audio vendor spe- cific verb is provided so firmware or other software can disable aux audio support and allow stopping the hd audio bus when an os is in an acti ve state. the default value of this bit is deter- mined by a bond option and may be determined by reading the device id. this bit only returns to its default value when a power on reset event is generated. 2.22.2. ?playback path? port behavior port f (aux audio in) input is routed to port d (?internal speakers?) and ports a&b (system head- phone jacks) through the analog mixer. 2.22.3. when port e presence detect = 0 ? presence detect for port e = 0 (nothing plugged in) ? port f, the ?aux audio in?, input is routed to port a, b, or d when that port is active. ? if either port a or port b is in use (port presence de tect = 1), port d, in ternal speakers, will be inactive (off) ? to save power, the power supply for port b will be active only if po rt b is in use (port b presence detect = 1). ? if neither port a nor port b is in use (port presence de tect = 0), port d, internal speakers, will be active and ports a and b will be inactive. ? eapd must not be forced low du e to the dock being absent or high when a dock is present. eapd is used to indicate if aux audio mode is in use. 2.22.4. when port e presence detect = 1 ? presence detect for port e = 1 (something plugged in) ? port f, the ?aux audio in?, input is routed to ports a, b ? port d is disabled ? if either port a or port b is in use (port pr esence detect = 1), that por t will be enabled and output the audio entering port f. ? to save power, the power supply for port b will be active only if po rt b is in use (port b presence detect = 1). ? if neither port a nor port b is in use (port presence detect = 0), ports a and b will be inactive and the audio on port f will play through the docked device (assu ming that the docked device signals that headphones are plugged into the device by using the port e presence detect.) ? eapd must not be forced low du e to the dock being absent or high when a dock is present. eapd is used to indicate if aux audio mode is in use.
idt confidential 30 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo figure 6. aux mode block diagram eapd (pin) aux support enable 1 1.default value for aux audio enable is determined by bond option. port e detect port b detect port a detect port c, d, f, dmic detect port d behavior port b behavior port a behavior 0 na na na na na disabled disabled disabled 1 0 na na na na widget controlled widget controlled widget controlled 1 1 000 na enabled (f to mix to d) disabled disabled 1 1 0 0 1 na disabled disabled enabled (f to mix to a) 1 1 0 1 0 na disabled enabled (f to mix to b) disabled 1 1 0 1 1 na disabled enabled (f to mix to b) enabled (f to mix to a) 1 1 1 0 0 na disabled disabled disabled 1 1 1 0 1 na disabled disabled enabled (f to mix to a) 1 1 1 1 0 na disabled enabled (f to mix to b) disabled 1 1 1 1 1 na disabled enabled (f to mix to b) enabled (f to mix to a) table 10. aux mode table ? vol mute vol vol mute mute vol mute pin complex pins 34/35/37/38 port d -34.5 to +12 db in 1.5 db steps port f boost +0/+10/+20/+30 db lo btl pin complex pins 13/14 port c port e port f class-ab pin complex pins 22/23 port a hp pin complex pins 25/26 port b hp mux ? analog beep digital pc beep mux ? analog beep digital pc beep mux ? analog beep digital pc beep vol mute vol mute dac0 port a dac1 vol -46.5 to 0 db in 1.5 db steps mute mixeroutvol dac1 mixeroutvol dac0 mux dac2 dac1 mixeroutvol dac0 mux dac2 dac1 mixeroutvol dac0 mux dac2 mixer and output ports forced on. output sent to btl amp by default but changed to hp if presence detect shows hp. hp jack hp jack internal speakers aux audio in (disabled) (disabled) (disabled) (disabled) (disabled) (disabled if port a, b, or e in use)
idt confidential 31 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 2.22.5. system diagrams docked ? normal mode d-mic hp spkr mic d b c f s hp a dock interface portable media player dac adc docked ? nothing plugged into docked player d-mic hp spkr mic d b c f s hp a portable media player port e pd=0 dock interface hp btl amp off if headphones plugged in
idt confidential 32 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 2.22.6. eapd since the aux audio mode overrides the default b ehavior but not the actual port settings when in reset, the logical state of the eapd pin must be overridden as well. when aux audio mode is enabled and the part is in reset as described ab ove, the logical state of eapd will be 1 (external amplifier powered up) unless held low by an external circuit. this ensures that audio pass-thru and analog pc_beep will be supported. 2.22.7. analog pc_beep analog pc_beep may be supported in aux audio mode. by default, analog pc_beep is disabled. if the codec is programmed to enable analog pc_b eep and aux audio mode is enabled, the next time reset is asserted, the ana log pc_beep pin will be mixed at each of the active outputs. 2.22.8. firmware/software requirements: the reconfiguration outlined in this chapter is enabled by default (without the help of firmware or os driver.) this autonomous mode does not interfere with normal operation. if it is desirable to stop the hd audio bus while the codec is in d3 under os control per dcn hda015-b, firmware must disable the aux audio mode support in the codec prior to loading the os. if aux audio mode is not disabled in the co dec, the codec will report to the os driver that stopping the bus clock while the codec is in d3 is not supported or not available. docked ? headphones plugged into do cked player d-mic hp spkr mic d b c f s hp a btl amp always off headphones on if plugged in portable media player port e pd=1 dock interface hp
idt confidential 33 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 3. characteristics 3.1. electrical specifications 3.1.1. absolute maximum ratings stresses above the ratings lis ted below can cause permanent dam age to the 92HD87. these rat- ings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other condi tions above those indicated in the operational sec- tions of the specifications is not implied. expo sure to absolute maximu m rating conditions for extended periods can affect pro duct reliability. electrical parame ters are gua ranteed only over the recommended operating temperature range. 3.1.2. recommended operating conditions item pin maximum rating analog maximum supply voltage avdd 6 volts digital maximum supply voltage dvdd 5.5 volts vrefout output current 5 ma voltage on any pin relative to ground vss - 0.3 v to vdd + 0.3 v operating temperature 0 o c to +70 o c storage temperature -55 o c to +125 o c soldering temperature soldering temperature information for all available in the package section of this datasheet. table 11. electrical speci fication: maximum ratings parameter min. typ. max. units power supplies dvdd_core 1.4 1.98 v dvdd_io (3.3v signaling) 3.135 3.3 3.465 v dvdd_io (1.5v signaling) 1.418 1.5 1.583 v power supply voltage digital - 3.3 v 3.135 3.3 3.465 v (note: with supply override enable bit set to force 5v operation.) analog - 4 v 3.8 4 4.2 v analog - 4.5 v 4.51 4.75 4.99 v analog - 5 v 4.75 5 5.25 v ambient operating temperature 0 +70 ?c case temperature t case (48-qfn) +95 ?c table 12. recommended operating conditions esd: the 92HD87 is an esd (electrostatic discharge) sens itive device. the human body and test equipment can accumulate and discharge electrostatic charges up to 4000 vo lts without detection. even though the 92HD87 implements internal esd protection circuitry, proper esd precautions sh ould be followed to avoid damaging the functionality or performance.
idt confidential 34 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 3.2. 92HD87 analog perfor mance characteristics (tambient = 25 oc, avdd = supply 5%, dvdd = 3.3v 5%, avss=dvss=0v; 20hz to 20khz swept sinusoidal input; sample frequency = 48 khz; 0 db = 1 vrms, 10k ? //50pf load, testbench char- acterization bw: 20 hz ? 20 khz, 0 db settings on all gain stages) parameter conditions avdd min typ max unit digital to analog converters resolution all 24 bits dynamic range 1 : pcm to all analog outputs -60db fs signal level 5v 4.75v 93 93 100 100 -db snr 2 - dac to all mono/line-out ports analog mixer disabled, pcm data 5v 4.75v 95 95 db thd+n 3 - dac to all mono/line-out ports analog mixer disabled, 0/-1/-3db fs signal, pcm data 5v 4.75v 83 83 dbr snr 2 - dac to all headphone ports analog mixer disabled, 10k ? load, pcm data 5v 4.75v 95 95 db thd+n 3 - dac to all headphone ports analog mixer disabled, 0/-1/-3db fs signal, 10k ? load, pcm data 5v 4.75v 83 83 dbr snr 2 - dac to all headphone ports analog mixer disabled, 32 ? load, pcm data 5v 4.75v 95 95 db thd+n 3 - dac to all headphone ports analog mixer disabled, 0db fs signal, 32 ? load, pcm data 5v 4.75v 68 68 dbr any analog input (adc) to dac crosstalk 10khz signal frequency. 0dbv signal applied to adc, dacs idle, ports enabled as output. all -65 - - db any analog input (adc) to dac crosstalk 1khz signal frequency see above all -65 - - db dac l/r crosstalk dac to lo or hp 20-15khz into 10k ? load all 65 db dac l/r crosstalk dac to hp 20-15khz into 32 ? load all 65 db gain error analog mixer disabled all 0.5 db interchannel gain mismatch analog mixer disabled all 0.5 db d/a digital filter pass band 4 all 20 - 21,000 hz d/a digital filter pass band ripple 5 0.1 +/- db d/a digital filter transition band all 21,000 - 31,000 hz d/a digital filter stop band all 31,000 - - hz d/a digital filter stop band rejection 6 all -100 - - db d/a out-of-band rejection 7 all -55 - - db group delay (48khz sample rate) all - - 1 ms attenuation, gain step size digital all - 0.75 - db dac offset voltage all - 10 20 mv deviation from linear phase all - 1 10 deg. analog outputs table 13. 92HD87 analog pe rformance characteristics
idt confidential 35 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo full scale all mono/line-outs dac pcm data 5v 4.75v 1.00 1.00 --vrms full scale all mono/line-outs dac pcm data 5v 4.75v 2.83 2.83 --vp-p all headphone capable outputs 32 ?? load 5v 4.75v 40 40 60 60 - mw (peak) amplifier output impedanc e mono/line outputs headphone outputs all 150 0.1 ohms external load capacitance mono/line outputs headphone outputs 220 pf analog inputs full scale input voltage 0db boost @4.75v (input voltage required for 0db fs output) 5v 4.75v 1.05 --vrms all analog inputs with boost 10db boost 5v 4.75v 0.320 --vrms all analog inputs with boost 20db boost 5v 4.75v 0.105 --vrms all analog inputs with boost 30db boost 5v 4.75v 0.032 --vrms boost gain accuracy all -1 db input impedance all - 50 - k ? input capacitance all - 15 - pf analog mixer dynamic range: pcm to all analog outputs -60db fs signal level analog beep enabled all other mixer inputs mute 5v 4.75v 93 93 snr 2 - all line-inputs to all line outputs all inputs unmuted, single line input driven by ate. 5v 4.75v 85 85 -d b thd+n 3 - all line-inputs to all line outputs 0db full scale input on one input, all others silent. 5v 4.75v 65 65 -d b r snr 2 - dac to all line outputs analog mixer enabled, pcm data, all others inputes mute. 5v 4.75v 93 93 -d b thd+n 3 - dac to all line-out ports analog mixer enabled, 0/-1/-3db fs signal, pcm data, all others inputes unmute/silent 5v 4.75v 83 83 dbr snr 2 - dac to all ports analog mixer enabled, pcm data, all others inputes unmute/silent. 5v 4.75v 85 85 -d b thd+n 3 - dac to all ports analog mixer enabled, 0db fs signal, pcm data, all others inputes unmute/silent 5v 4.75v 75 75 -d b r attenuation, gain step size analog all - 1.5 - db analog to digital converter resolution all 24 bits parameter conditions avdd min typ max unit table 13. 92HD87 analog pe rformance characteristics
idt confidential 36 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo full scale input voltage 0db boost (input voltage required to generate 0dbfs per aes 17) 5v 4.75v 1.05 1.05 dynamic range 1 , all analog inputs to a/d high pass filer enabled, -60db fs, no boost 5v 4.75v 86 86 92 92 db snr 2 - all analog inputs to a/d high pass filter enabled 5v 4.75v 86 86 -d b full scale input voltage 20db boost (input voltage required to generate 0dbfs per aes 17) 5v 4.75v 0.105 0.105 dynamic range 1 , all analog inputs to a/d 20db boost high pass filter enabled, -60db fs 5v 4.75v 81 81 thd+n 3 all analog inputs to a/d high pass filter enabled, -1/-3db fs signal level 5v 4.75v 78 78 db thd+n 3 all analog inputs to a/d 20db boost, high pass filter enabled, -1/-3db fs signal level 5v 4.75v 72 72 db analog frequency response 8 all 10 - 30,000 hz a/d digital filter pass band 4 all 20 - 21,000 hz a/d digital filter pass band ripple 5 all 0.1 +/- db a/d digital filter transition band all 21,000 - 31,000 hz a/d digital filter stop band all 31,000 - - hz a/d digital filter stop band rejection 6 all -100 - - db group delay 48 khz sample rate all - - 1 ms any unselected analog input to adc crosstalk 10khz signal frequency all -65 - - db any unselected analog input to adc crosstalk 1khz signal frequency all -65 - - db adc l/r crosstalk any selected input to adc 20-15khz all -65 db dac to adc crosstalk dac output 0dbfs. all outputs loaded. input to adc open. 20-15khz all -65 db spurious tone rejection 9 all - -100 - db attenuation, gain step size (analog) all - 1.5 - db interchannel gain mismatch adc all - - 0.5 db power supply power supply rejection ratio 10khz all - -60 - db power supply rejection ratio 1khz all - -70 - db d0 didd 10 3.3v, 1.8v, 1.5v 25 ma d0 aidd 10 4.75v 60 ma d0 didd 11 3.3v, 1.8v, 1.5v 20 ma d0 aidd 11 4.75v 34 ma d1 didd 12 3.3v, 1.8v, 1.5v 7 ma parameter conditions avdd min typ max unit table 13. 92HD87 analog pe rformance characteristics
idt confidential 37 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo d1 aidd 12 4.75v 30 ma d2 didd 3.3v, 1.8v, 1.5v 7 ma d2 aidd 4.75v 15 ma d3 (beep enabled) didd 13 3.3v, 1.8v, 1.5v 2 ma d3 (beep enabled) aidd 13 4.75v 10 ma d3 didd 13 3.3v, 1.8v, 1.5v 2 ma d3 aidd 13 4.75v 5 ma d3cold didd 13 3.3v, 1.8v, 1.5v 1 ma d3cold aidd 13 4.75v 5 ma vendor d4 didd 3.3v, 1.8v, 1.5v 0.4 ma vendor d4 aidd 4.75v 5 ma vendor d5 didd 3.3v, 1.8v, 1.5v 0.4 ma vendor d5 aidd 4.75v 0.6 ma one stereo adc didd 3.3v, 1.8v, 1.5v 4 ma one stereo adc aidd 4.75 8 ma one stereo dac didd 3.3v, 1.8v, 1.5v 4 ma one stereo dac aidd 4.75v 6 ma voltage reference outputs vrefout 14 all - 0.5 x avdd -v vrefout drive all 1.6 ma vrefilt (vag) all 0.45 x avdd v phased locked loop pll lock time all 96 200 usec pll (or hd audio bit clk) 24mhz clock jitter all 150 500 psec esd / latchup latch-up as described in jesd78a class ii all 70 degc esd - human body model as described in jesd22-a114-b all 2k 3k v charged device model as described in jesd22-c101 all 500 1k v 1.dynamic range is the ratio of the full sca le signal to the noise output with a -60dbfs signal as defined in aes17 as snr in t he presence of signal and outlined in aes6id, measured ?a weighted? over 20 hz to 20 khz bandwidth 2.ratio of full scale signal to idle channel noise output is measured ?a weighted? over a 20 hz to a 20 khz bandwidth. (aes17-1991 idle channel noise or eiaj cp-307 signal-to-noise ratio). 3.thd+n ratio as defined in aes17 and out lined in aes6id,non-weighted, over 20 hz to 20 khz bandwidth.r esults at the jack are dependent on external components and will likely be 1 - 2db worse. 4.peak-to-peak ripple over passband meets 0.125db limits, 48 khz or 44.1 khz sample frequency. 1db limit. 5.peak-to-peak ripple over passband meets 0.125db limit s, 48 khz or 44.1 khz sample frequency. 1db limit. 6.stop band rejection determines f ilter requirements. out-of-band re jection determines audible noise. 7.the integrated out-of-band noise generated by the dac proc ess, during normal pcm audio playback, over a bandwidth 28.8 to 100 khz, with respect to a 1 vrms dac output. 8. 1db limits for line output & 0 db gain, at -20dbv parameter conditions avdd min typ max unit table 13. 92HD87 analog pe rformance characteristics
idt confidential 38 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 3.3. ac timing specs 3.3.1. hd audio bus timing figure 7. hd audio bus timing 9.spurious tone rejection is test ed with adc dither enabled and compared to adc performance without dither. 10.all functions/converters active, pin complexes enabled, two fd x streams, line (10kohm) loads. add 24ma analog current per stereo 32 ohm headphone. 11.one stereo dac and corresponding pin widgets enabled (playback mode) 12.mixer enabled 13.idle measurement d3 set for minimum clicks/pops (biases and min. amps. on) 14.can be set to 0.5 or 0.8 avdd. parameter definition symbol min typ max units bclk frequency average bclk frequency 23.997 6 24.0 24.002 4 mhz bclk period period of bclk including jitter tcyc 41.163 41.67 42.171 ns bclk high phase high phase of bclk t_high 17.5 24.16 ns bclk low phase low phase of bclk t_low 17.5 24.16 ns bclk jitter bclk jitter 150 500 ps sdi delay time after rising edge of bclk that sdi becomes valid t_tco 3 11 ns sdo setup setup for sdo at both rising and falling edges of bclk t_su 5 ns sdo hold hold for sdo at both rising and falling edges of bclk t_h 5 ns table 14. hd audio bus timing
idt confidential 39 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 3.3.2. digital microphone timing 3.3.3. class-ab btl amplifier performance 3.3.4. capless headphone supply characteristics parameter definition symbol min typ max units dmic_clk frequency average dmic_clk frequency 1.176 2.352 4.704 mhz dmic_clk period period of dmic_clk tdmic_cyc 850.34 425.17 212.59 ns dmic_clk jitter dmic_clk jitter 5000 ps dmic data setup setup for the microphone data at both rising and falling edges of dmic_clk tdmic_su 5 ns dmic data hold hold for the microphone data at both rising and falling edges of dmic_clk tdmic_h 5 ns table 15. digital mic timing parameter min typ max unit output power (btl 4 ohm, 5v - continuous average power)) 2 w output power (btl 8 ohm, 5v - continuous average power)) 1 w amplifier efficiency ?????? ?? 5v, 2w) 1 1. amplifier efficiency includes circuits specific to the btl ampl ifier audio path such as temperature limit, short circuit, and other support circuits. 60 % thd+n (btl 4 or 8 ohm, 5v, fs) 1% frequency response 20 - 20k hz output voltage noise 50 uv shutdown current 0.6 ma table 16. class-ab btl amplifier performance parameter min typ max unit ldo idle current 12m a cap-less headphone amp idle current 2 3 charge pump idle current 46m a charge pump shutdown time 1m s charge pump start-up time 10 ms frequency 384 khz c1/c2 cap value 2.2 uf table 17. capless headphone supply
idt confidential 40 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 4. functional block diagrams port c is input only on the tb revision. ra revision is output capable . figure 8. functional block diagram stream & channel select dac 0 stream & channel select hd audio link logic vol dac 1 digital mute digital mute vendor specific mux loop 1 adc1 pin 4 dmic_0 dmic_0 mux stream & channel select ? vol mute vol mute vol mute vol mute analog pc_beep digital microphone volume and mute is done after the adc but shown here and in widget list as same as analog path. dac0 dac1 mixer boost +0/+10/+20/+30 db dmic pin complex pins 19/20 port c mic bias pin complex pins 39/41/43/44 port d adc0 stream & channel select vol gain mute 0 to +22.5 db in 1.5 db steps adc1 vol gain mute 0 to +22.5 db in 1.5 db steps -34.5 to +12 db in 1.5 db steps boost +0/+10/+20/+30 db port c lo 0,-6,-12,-18db port f boost +0/+10/+20/+30 db port f lo stereo btl pin complex pins 17/18 port c port f class-ab vol pin complex pins 28/29 port a boost +0/+10/+20/+30 db port a hp pin complex pins 31/32 port b hp cap-less port c mux mixer port f dmic0 port a port c mux mixer port f dmic0 port a mux ? analog beep digital pc beep mux ? analog beep digital pc beep mux ? analog beep digital pc beep mux ? analog beep digital pc beep mux ? analog beep digital pc beep vol mute vol mute dac0 port a dac1 mic bias vol -46.5 to 0 db in 1.5 db steps mute mixeroutvol dac1 mixeroutvol dac0 mux dac1 mixeroutvol dac0 mux dac1 mixeroutvol dac0 mux dac1 mixeroutvol dac0 mux dac1 mixeroutvol dac0 mux
idt confidential 41 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 5. widget information and supported command verbs port c is input only on the tb revision. ra revision is output capable figure 9. widget diagram hda link nid = 1eh nid = 20h vsw adc0 mux adc1 mux dac0 adc0 nid = 15h dmic0 nid = 11h port b port a nid = 0ah analog* dac0 nid = 13h volume mute hp mixer nid = 17h adc0 mux volume mute dmic0 mixer nid = 18h vol nid = 12h adc1 nid = 16h dac1 mixeroutvol nid = 0bh port c bias nid = 0ch port d nid = 0dh vsw nid = 0eh port f nid = 0fh dac1 nid = 14h volume mute 10/20/30 0 to 22.5db 1.5db step -95.25 to 0db 0.75db step -95.25 to 0db 0.75db step nid = 1dh nid = 1fh vsw pc_beep nid = 21h digital nid = 1ah hp btl pc_beep (pin 12) mute volume nid = 1bh ? -34.5 to +12db in 1.5db steps dac0 dac1 in vol 10/20/30 in vol 10/20/30 lo lo port c port f adc1 mux volume mute 0 to 22.5db 1.5db step nid = 19h port f port c 0,-6,-12,-18db vsv vsw nid = 10h dac0 dac1 mixeroutvol dac0 dac1 mixeroutvol dac0 dac1 mixeroutvol dac0 dac1 mixeroutvol vsw vsw dmic0 dmic0 mixer port c port f port a port a port a vsw nid = 22h mute volume mute volume mute volume mute volume port f port c mute volume mute volume dac0 port a dac1 to all ports enabled as an output to all ports enabled as an output nid = 1ch mixeroutvol volume -46.5 to 0db in 1.5db steps mixer mixeroutvol mute bias in vol 10/20/30 vsw vsw vsw
idt confidential 42 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 6. port configurations port c is input only on the tb revision. ra revision is output capable figure 10. port configurations a hp rear c mic,li hp b front f mic (fixed bias) desktop 1 f lo rear a mic,hp hp b front c mic / li desktop 2 a hp rear c mic hp b front f li desktop 3 chassis speaker a m p d chassis speaker d a mic / li /hp hp / lo b side digital mic array c mic / li hp using external amp f dock mobile a m p chassis speaker d a m p internal speakers d a m p
idt confidential 43 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 6.1. pin configuration defa ult register settings the following table shows the pin widget configurati on default settings. mobile 3-jack implementa- tion with 3 hp jacks in front and 2 jacks in rear. the internal speaker is redirected from the front (green) headphone jack, while the other (black) headphone jack and microphone jack may be used for rtc. pin name port location device connection color misc pin name port portapin connect to jack 00b mainboard front 2h hp out 2h 1/8 inch jack 1h green 4h jack detect override=0 3h fh portbpin connect to jack 00b mainboard front 2h hp out 2h 1/8 inch jack 1h black 1h jack detect override=0 1h 0h portcpin connect to jack 00b mainboard front 2h mic in ah 1/8 inch jack 1h pink 9h jack detect override=0 2h 0h portdpin internal 10b na 010000b speaker 1h other analog 7h unknown 0h jack detect override=0 3h 0h portfpin connect to jack 00b mainboard rear 1h line in 8h 1/8 inch jack 1h pink 9h jack detect override=0 4h 0h digmic0pin internal 10b internal 010000b mic in ah atapi 3h unknown 0h jack detect override=0 4h 1h table 18. pin configuration default settings port c is input only on the tb revision. ra revision is output capable
idt confidential 44 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 7. widget information there are two types of responses: solicited and un solicited. solicited responses are provided as a direct response to an issued command and will be provided in the frame immediately following the command. unsolicited responses are provided by the codec independent of any command. unso- licited responses are the result of codec events su ch as a jack insertion detection. the formats for solicited responses and un solicited responses are shown in the tables below. the ?tag? field in bits [31:28] of the unsolicited response identify the event. 7.1. widget list bits [39:32] bits [31:28] bits [27:20] bits[19:16] bits [15:0] reserved codec address nid verb id (4-bit) payload data (16-bit) table 19. command format for verb with 4-bit identifier bits [39:32] bits [31:28] bits [27:20] bits[19:8] bits [7:0] reserved codec address nid verb id (12-bit) payload data (8-bit) table 20. command format for verb with 12-bit identifier bit [35] bit [34] bits [33:32] bits[31:0] valid (valid = 1) unsol = 0 reserved response table 21. solicited response format bit [35] bit [34] bits [33:32] bits[31:28] bits [27:0] valid (valid = 1) unsol = 1 reserved tag response table 22. unsolicited response format id widget name description 00h root root node 01h afg audio function group 0ah port a port a pin widget (capless headphone) 0bh port b port b pin widget (capless headphone) 0ch port c port c pin widget (line in/out, mic) (line in, mic on tb revision) 0dh port d port d pin widget (btl output - eapd control) 0eh vendor reserved vendor reserved 0fh port f port f pin widget (line in/out, mic) 10h vendor reserved vendor reserved 11h digmic0 digital microphone 0 pin widget table 23. high definition audio widget
idt confidential 45 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 12h vendor reserved vendor reserved 13h dac0 stereo output converter to dac 14h dac1 stereo output converter to dac 15h adc0 stereo input converter to adc 16h adc1 stereo input converter to adc 17h adc0mux adc0 mux with volume and mute 18h adc1mux adc1 mux with volume and mute 19h vendor reserved vendor reserved 1ah vendor reserved vendor reserved 1bh mixer input mixer (input ports, dacs, analog pc_beep) 1ch mixeroutvol volume control for analog mixer 1dh vendor reserved vendor reserved 1eh vendor reserved vendor reserved 1fh vendor reserved vendor reserved 20h vendor reserved vendor reserved 21h digbeep digital pc beep 22h vendor reserved vendor reserved id widget name description table 23. high definition audio widget
idt confidential 46 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8. widgets 8.1. reset key abbreviation description por power on reset. safg single afg reset - one single write to the reset verb in the afg node. dafg double afg reset - two consecutive single afg resets with only idle frames (if any) and no link re- sets between. s&dafg single and double afg reset - either one will cause reset. lr link reset - level sensitive reset anytime the hda reset is set low. elr exiting link reset - edge sensitive reset any time the hda reset transitions from low to high. ulr unexpected link reset - level sensitive reset any time the hda reset is set low when the clkstopok indicator is currently set to 0. ps power state change - reset anytime the actual power state changes for the widget in question. 8.2. root (nid = 00h): vendorid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0000h field name bits r/w default reset vendor 31:16 r 111dh n/a vendor id. devicefix 15:8 r see below n/a device id. deviceprog 7:0 r see below n/a device id. device 92HD87b1 92HD87b2 92HD87b3 92HD87b4 device id 76d1h 76d9 76d1h 76d9h
idt confidential 47 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.2.1. root (nid = 00h): revid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0002h field name bits r/w default reset rsvd 31:24 r 00h n/a (hard-coded) reserved. major 23:20 r 1h n/a (hard-coded) major rev number of compliant hd audio spec. minor 19:16 r 0h n/a (hard-coded) minor rev number of compliant hd audio spec. revisionfix 15:12 r xh n/a (hard-coded) vendor's rev number for this device. revisionprog 11:8 r xh n/a (hard-coded) vendor's rev number for this device. steppingfix 7:4 r xh n/a (hard-coded) vendor stepping number within the vendor revid. steppingprog 3:0 r xh n/a (hard-coded) vendor stepping number within the vendor revid. 8.2.2. root (nid = 00h): nodeinfo reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0004h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved.
idt confidential 48 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo startnid 23:16 r 01h n/a (hard-coded) starting node number (nid) of first function group rsvd1 15:8 r 00h n/a (hard-coded) reserved. totalnodes 7:0 r 01h n/a (hard-coded) total number of nodes 8.3. afg (nid = 01h): nodeinfo reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0004h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. startnid 23:16 r 0ah n/a (hard-coded) starting node number for function group subordinate nodes. rsvd1 15:8 r 00h n/a (hard-coded) reserved. totalnodes 7:0 r 19h n/a (hard-coded) total number of nodes. 8.3.1. afg (nid = 01h): fgtype reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0005h field name bits r/w default reset
idt confidential 49 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:9 r 000000h n/a (hard-coded) reserved. unsol 8 r 1h n/a (hard-coded) unsolicited response supported: 1 = yes, 0 = no. nodetype 7:0 r 1h n/a (hard-coded) function group type: 00h = reserved 01h = audio function group 02h = vendor defined modem function group 03h-7fh = reserved 80h-ffh = vendor defined function group 8.3.2. afg (nid = 01h): afgcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0008h field name bits r/w default reset rsvd3 31:17 r 00h n/a (hard-coded) reserved. beepgen 16 r 1h n/a (hard-coded) beep generator present: 1 = yes, 0 = no. rsvd2 15:12 r 0h n/a (hard-coded) reserved. inputdelay 11:8 r dh n/a (hard-coded) typical latency in frames. number of samples between when the sample is re- ceived as an analog signal at the pin and when the digital representation is transmitted on the hd audio link. rsvd1 7:4 r 0h n/a (hard-coded) reserved.
idt confidential 50 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo outputdelay 3:0 r dh n/a (hard-coded) typical latency in frames. number of samples between when the signal is re- ceived from the hd audio link and when it appears as an analog signal at the pin. 8.3.3. afg (nid = 01h): pcmcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ah field name bits r/w default reset rsvd2 31:21 r 000h n/a (hard-coded) reserved. b32 20 r 0h n/a (hard-coded) 32 bit audio format support: 1 = yes, 0 = no. b24 19 r 1h n/a (hard-coded) 24 bit audio format support: 1 = yes, 0 = no. b20 18 r 1h n/a (hard-coded) 20 bit audio format support: 1 = yes, 0 = no. b16 17 r 1h n/a (hard-coded) 16 bit audio format support: 1 = yes, 0 = no. b8 16 r 0h n/a (hard-coded) 8 bit audio format support: 1 = yes, 0 = no. rsvd1 15:12 r 0h n/a (hard-coded) reserved. r12 11 r 0h n/a (hard-coded) 384khz rate support: 1 = yes, 0 = no. r11 10 r 1h n/a (hard-coded) 192khz rate support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 51 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo r10 9 r 0h n/a (hard-coded) 176.4khz rate support: 1 = yes, 0 = no. r9 8 r 1h n/a (hard-coded) 96khz rate support: 1 = yes, 0 = no. r8 7 r 1h n/a (hard-coded) 88.2khz rate support: 1 = yes, 0 = no. r7 6 r 1h n/a (hard-coded) 48khz rate support: 1 = yes, 0 = no. r6 5 r 1h n/a (hard-coded) 44.1khz rate support: 1 = yes, 0 = no. r5 4 r 0h n/a (hard-coded) 32khz rate support: 1 = yes, 0 = no. r4 3 r 0h n/a (hard-coded) 22.05khz rate support: 1 = yes, 0 = no. r3 2 r 0h n/a (hard-coded) 16khz rate support: 1 = yes, 0 = no. r2 1 r 0h n/a (hard-coded) 11.025khz rate support: 1 = yes, 0 = no. r1 0 r 0h n/a (hard-coded) 8khz rate support: 1 = yes, 0 = no. 8.3.4. afg (nid = 01h): streamcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000bh field name bits r/w default reset
idt confidential 52 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. ac3 2 r 0h n/a (hard-coded) ac-3 formatted data support: 1 = yes, 0 = no. float32 1 r 0h n/a (hard-coded) float32 formatted data support: 1 = yes, 0 = no. pcm 0 r 1h n/a (hard-coded) pcm-formatted data support: 1 = yes, 0 = no. 8.3.5. afg (nid = 01h): inampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000dh field name bits r/w default reset mute 31 r 0h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 27h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 03h n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved.
idt confidential 53 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo offset 6:0 r 00h n/a (hard-coded) indicates which step is 0db 8.3.6. afg (nid = 01h): pwrstatecap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000fh field name bits r/w default reset epss 31 r 1h n/a (hard-coded) extended power states support: 1 = yes, 0 = no. clkstop 30 r 1h n/a (hard-coded) d3 clock stop support: 1 = yes, 0 = no. s3d3coldsup 29 r 1h n/a (hard-coded) codec state intended during system s3 state: 1 = d3hot, 0 = d3cold. on yb revs & prior, this was called lpd3sup & default was 0h rsvd 28:5 r 000000h n/a (hard-coded) reserved. d3coldsup 4 r 1h n/a (hard-coded) d3cold power state support: 1 = yes, 0 = no. d3sup 3 r 1h n/a (hard-coded) d3 power state support: 1 = yes, 0 = no. d2sup 2 r 1h n/a (hard-coded) d2 power state support: 1 = yes, 0 = no. d1sup 1 r 1h n/a (hard-coded) d1 power state support: 1 = yes, 0 = no. d0sup 0 r 1h n/a (hard-coded) d0 power state support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 54 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.3.7. afg (nid = 01h): gpiocnt reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0011h field name bits r/w default reset gpiwake 31 r 1h n/a (hard-coded) wake capability. assuming the wake enable mask controls are enabled, gpio's configured as inputs can cause a wake (generate a status change event on the link) when there is a change in level on the pin. gpiunsol 30 r 1h n/a (hard-coded) gpio unsolicited response support: 1 = yes, 0 = no. rsvd 29:24 r 00h n/a (hard-coded) reserved. numgpis 23:16 r 00h n/a (hard-coded) number of gpi pins supported by function group. numgpos 15:8 r 00h n/a (hard-coded) number of gpo pins supported by function group. numgpios 7:0 r 03h n/a (hard-coded) number of gpio pins supported by function group. 8.3.8. afg (nid = 01h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no.
idt confidential 55 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 02h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 7fh n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 7fh n/a (hard-coded) indicates which step is 0db 8.3.9. afg (nid = 01h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd3 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this function group have been reset. cleared by pwrstate 'get' to this widget. clkstopok 9 r 1h por - dafg - ulr bit clock can currently be removed: 1 = yes, 0 = no. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. field name bits r/w default reset
idt confidential 56 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd2 7 r 0h n/a (hard-coded) reserved. act 6:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3 r 0h n/a (hard-coded) reserved. set 2:0 rw 3h por - dafg - lr current power state setting for this widget. 8.3.10. afg (nid = 01h): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable: 1 = enabled, 0 = disabled. rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 8.3.11. afg (nid = 01h): gpio reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 715h get f1500h field name bits r/w default reset
idt confidential 57 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. data2 2 rw 0h por - dafg - ulr data for gpio2. if this gpio bit is configured as sticky (edge-sensitive) input, it can be cleared by writing "0". for details of read back value, refer to hd audio spec. section 7.3.3.22 data1 1 rw 0h por - dafg - ulr data for gpio1. if this gpio bit is configured as sticky (edge-sensitive) input, it can be cleared by writing "0". for details of read back value, refer to hd audio spec. section 7.3.3.22 data0 0 rw 0h por - dafg - ulr data for gpio0. if this gpio bit is configured as sticky (edge-sensitive) input, it can be cleared by writing "0". for details of read back value, refer to hd audio spec. section 7.3.3.22 8.3.12. afg (nid = 01h): gpioen reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 716h get f1600h field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. mask2 2 rw 0h por - dafg - ulr enable for gpio2: 0 = pin is disabled (hi-z state); 1 = pin is enabled; behavior determined by gpio direction control mask1 1 rw 0h por - dafg - ulr enable for gpio1: 0 = pin is disabled (hi-z state); 1 = pin is enabled; behavior determined by gpio direction control mask0 0 rw 0h por - dafg - ulr enable for gpio0: 0 = pin is disabled (hi-z state); 1 = pin is enabled; behavior determined by gpio direction control
idt confidential 58 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.3.13. afg (nid = 01h): gpiodir reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 717h get f1700h field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. control2 2 rw 0h por - dafg - ulr direction control for gpio2: 0 = gpio is configured as input; 1 = gpio is con- figured as output control1 1 rw 0h por - dafg - ulr direction control for gpio1: 0 = gpio is configured as input; 1 = gpio is con- figured as output control0 0 rw 0h por - dafg - ulr direction control for gpio0: 0 = gpio is configured as input; 1 = gpio is con- figured as output 8.3.14. afg (nid = 01h): gpiowakeen reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 718h get f1800h field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. w2 2 rw 0h por - dafg - ulr wake enable for gpio2: 0 = wake-up event is disabled; 1 = when hd audio link is powered down (rst# is asserted), a wake-up event will trigger a status change request event on the link.
idt confidential 59 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo w1 1 rw 0h por - dafg - ulr wake enable for gpio1: 0 = wake-up event is disabled; 1 = when hd audio link is powered down (rst# is asserted), a wake-up event will trigger a status change request event on the link. w0 0 rw 0h por - dafg - ulr wake enable for gpio0: 0 = wake-up event is disabled; 1 = when hd audio link is powered down (rst# is asserted), a wake-up event will trigger a status change request event on the link. 8.3.15. afg (nid = 01h): gpiounsol reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 719h get f1900h field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. enmask2 2 rw 0h por - dafg - ulr unsolicited enable mask for gpio2. if set, and the unsolicited response con- trol for this widget has been enabled, an unsolicited response will be sent when gpio2 is configured as input and changes state. enmask1 1 rw 0h por - dafg - ulr unsolicited enable mask for gpio1. if set, and the unsolicited response con- trol for this widget has been enabled, an unsolicited response will be sent when gpio1 is configured as input and changes state. enmask0 0 rw 0h por - dafg - ulr unsolicited enable mask for gpio0. if set, and the unsolicited response con- trol for this widget has been enabled, an unsolicited response will be sent when gpio0 is configured as input and changes state. 8.3.16. afg (nid = 01h): gpiosticky reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71ah field name bits r/w default reset
idt confidential 60 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo get f1a00h field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. mask2 2 rw 0h por - dafg - ulr gpio2 input type (when configured as input): 0 = non-sticky (level-sensitive); 1 = sticky (edge-sensitive). mask1 1 rw 0h por - dafg - ulr gpio1 input type (when configured as input): 0 = non-sticky (level-sensitive); 1 = sticky (edge-sensitive). mask0 0 rw 0h por - dafg - ulr gpio0 input type (when configured as input): 0 = non-sticky (level-sensitive); 1 = sticky (edge-sensitive). 8.3.17. afg (nid = 01h): subid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 723h 722h 721h 720h get f2300h / f2200h / f2100h / f2000h field name bits r/w default reset subsys3 31:24 rw 00h por subsystem id (byte 3) subsys2 23:16 rw 00h por subsystem id (byte 2) subsys1 15:8 rw 01h por subsystem id (byte 1) assembly 7:0 rw 00h por assembly id (not applicable to codec vendors). 8.3.16. afg (nid = 01h): gpiosticky reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0)
idt confidential 61 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.3.18. afg (nid = 01h): gpioplrty reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 770h get f7000h field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. gp2 2 rw 1h por - dafg - ulr gpio2 polarity: if configured as output or non-sticky input: 0 = inverting 1 = non-inverting if configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected gp1 1 rw 1h por - dafg - ulr gpio1 polarity: if configured as output or non-sticky input: 0 = inverting 1 = non-inverting if configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected gp0 0 rw 1h por - dafg - ulr gpio0 polarity: if configured as output or non-sticky input: 0 = inverting 1 = non-inverting if configured as sticky input: 0 = falling edges will be detected 1 = rising edges will be detected 8.3.19. afg (nid = 01h): gpiodrive reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 771h get f7100h
idt confidential 62 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. od2 2 rw 0h por - dafg - ulr gpio2 drive mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float for 1). od1 1 rw 0h por - dafg - ulr gpio1 drive mode: 0 = push-pull (drive 0 and 1); 1 = open drain (drive 0, float for 1). od0 0 rw 0h por - dafg - ulr gpio0 drive mode: 0 = push-pull (drive 0 and 1); 1 = open-drain (drive 0, float for 1). 8.3.20. afg (nid = 01h): dmic reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 778h get f7800h field name bits r/w default reset rsvd 31:5 r 0000000h n/a (hard-coded) reserved. mono0 4 rw 0h por dmic0 mono select: 0 = stereo operati on, 1 = mono operation (left channel du- plicated to the right channel). phadj 3:2 rw 0h por selects what phase of the dmic clock the data should be latched: 0h = left data rising edge/right data falling edge 1h = left data center of high/right data center of low 2h = left data falling edge/right data rising edge 3h = left data center of low/right data center of high
idt confidential 63 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rate 1:0 rw 2h por selects the dmic clock rate: 0h = 4.704mhz 1h = 3.528mhz 2h = 2.352mhz 3h = 1.176mhz. 8.3.21. afg (nid = 01h): dacmode reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 780h get f8000h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. sdmsettledisable 7 rw 0h por - s&dafg - lr sdm wait-to-settle disable: 1 = at mute, the sdm switches to the mute pattern immediately 0 = at mute, the sdm switches to the mute pattern after settling (can take up to ~45ms) sdmcoeffsel 6 rw 0h por - s&dafg - lr dac sdm coefficient select (stages 1, 2, 3): 1 = 1/16, 1/2, 1/4 0 = 1/16, 1/4, 1/2 sdmlfhalf 5 rw 0h por - s&dafg - lr dac sdm local feedback coefficient select: 1 = 1/4096, 0 = 1/2048. sdmlfdisable 4 rw 0h por - s&dafg - lr dac sdm local feedback disable: 1 = local feedback disabled, 0 = local feed- back enabled. invertvalid 3 rw 0h por - s&dafg - lr dac valid invert: 1 = 7.056mhz valid strobe is inverted, 0 = 7.056mhz valid strobe is not inverted. field name bits r/w default reset
idt confidential 64 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo invertdata 2 rw 0h por - s&dafg - lr dac data invert: 1 = 1-bit outputs are inverted, 0 = 1-bit outputs are not invert- ed. atten6dbdisable 1 rw 0h por - s&dafg - lr disable built-in -6db digital attenuation: 1 = -6db disabled, 0 = -6db enabled. fade 0 rw 1h por - s&dafg - lr dac gain fade enable: 1 = gain will be slowly faded from old value to new value (~10ms) 0 = gain will jump immediately to new value. 8.3.22. afg (nid = 01h): adcmode reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 784h get f8400h field name bits r/w default reset rsvd2 31:4 r 0000000h n/a (hard-coded) reserved. invertvalid 3 rw 0h por - s&dafg - lr adc valid invert: 1 = 14.112mhz valid strobe is inverted, 0 = 14.112mhz valid strobe is not inverted. invertdata 2 rw 0h por - s&dafg - lr adc data invert: 1 = 1-bit inputs are inverted, 0 = 1-bit inputs are not inverted. rsvd1 1:0 r 0h n/a (hard-coded) reserved. 8.3.23. afg (nid = 01h): eapd reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 788h get f8800h field name bits r/w default reset
idt confidential 65 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd4 31:15 r 00000h n/a (hard-coded) reserved. hpbsdinv 14 rw 0h por hp amp shutdown invert: 0 = amp will power down (or mute) when eapd pin is low 1 = amp will power down (or mute) when eapd pin is high hpbsdmode 13 rw 1h por hp amp shutdown mode: 0 = amp will mute when disabled 1 = amp will enter a low power state when disabled hpbsd 12 rw 0h por hp amp shutdown control select: 0 = amp controlled by eapd pin only 1 = amp controlled by power state only rsvd3 11 r 0h n/a (hard-coded) reserved. hpasdinv 10 rw 0h por hp amp shutdown invert: 0 = amp will power down (or mute) when eapd pin is low 1 = amp will power down (or mute) when eapd pin is high hpasdmode 9 rw 1h por hp amp shutdown mode: 0 = amp will mute when disabled 1 = amp will enter a low power state when disabled hpasd 8 rw 0h por hp amp shutdown control select: 0 = amp controlled by eapd pin only 1 = amp controlled by power state only rsvd2 7 r 0h n/a (hard-coded) reserved. btlsdinv 6 rw 0h por btl amp shutdown invert: 0 = amp will power down (or mute) when eapd pin is low 1 = amp will power down (or mute) when eapd pin is high
idt confidential 66 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo btlsdmode 5 rw 1h por btl amp shutdown mode: 0 = amp will mute when disabled 1 = amp will enter a low power state when disabled btlsd 4 rw 0h por btl amp shutdown control select: 0 = amp controlled by eapd pin only 1 = amp controlled by power state only rsvd1 3:2 r 0h n/a (hard-coded) reserved. pinmode 1:0 rw 0h por eapd pin mode: 00b = open drain i/o (value at pin is wi red-and of eapd bit and external sig- nal) 01b = cmos output (value of eapd bit is forced at pin) 1xb = cmos input (external signal cont rols internal amps, eapd bit ignored) 8.3.24. afg (nid = 01h): portuse reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7c0h get fc000h field name bits r/w default reset rsvd 31:7 r 0000000h n/a (hard-coded) reserved. mono 6 rw 1h por mono usage: 0 = connected as an output, 1 = either not connected or connect- ed as an input. portf 5 rw 1h por port f usage: 0 = connected as an output, 1 = either not connected or connect- ed as an input. field name bits r/w default reset
idt confidential 67 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo porte 4 rw 1h por port e usage: 0 = connected as an output, 1 = either not connected or connect- ed as an input. port e not supported. portd 3 rw 1h por port d usage: 0 = connected as an output, 1 = either not connected or connect- ed as an input. portc 2 rw 1h por port c usage: 0 = connected as an output, 1 = either not connected or connect- ed as an input. portb 1 rw 1h por port b usage: 0 = connected as an output, 1 = either not connected or connect- ed as an input. porta 0 rw 1h por port a usage: 0 = connected as an output, 1 = either not connected or connect- ed as an input. 8.3.25. afg (nid = 01h): vspwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7d8h get fd800h field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. d5 1 rw 0h por - elr vendor specific d5 power state, only entered once the part is already in d3cold (this bit must be set before the command to enter d3cold). if set, this bit over- rides the d4 bit (bit 0). includes the power savings of d4, but additionally pow- ers down gpio pins, the vag amp, and the hp amps. exits this power state via por or rising edge of link reset. field name bits r/w default reset
idt confidential 68 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo d4 0 rw 0h por - elr vendor specific d4 power state, only entered once the part is already in d3cold (this bit must be set before the command to enter d3cold). if the d5 bit (bit 1) is set, this bit is overridden. includes the power savings of d3cold, but addi- tionally powers down the hda interface (no responses). exit this power state via por or rising edge of link reset. 8.3.26. afg (nid = 01h): anaport reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7edh 7ech get fec00h field name bits r/w default reset rsvd2 31:7 r 0000000h n/a (hard-coded) reserved. monopwd 6 rw 0h por - s&dafg - ulr power down mono output. fpwd 5 rw 0h por - s&dafg - ulr power down port f. epwd 4 rw 0h por - s&dafg - ulr power down port e. port e not supported. dpwd 3 rw 0h por - s&dafg - ulr power down port d. cpwd 2 rw 0h por - s&dafg - ulr power down port c. bpwd 1 rw 0h por - s&dafg - ulr power down port b. apwd 0 rw 0h por - s&dafg - ulr power down port a. field name bits r/w default reset
idt confidential 69 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.3.27. afg (nid = 01h): anabeep reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7eeh get fee00h field name bits r/w default reset rsvd 31:3 r 0000000h n/a (hard-coded) reserved. gain 2:1 rw 3h por - dafg - elr analog pc beep gain: 0h = -24db, 1h = -18db, 2h = -12db, 3h = -6db. enable 0 rw 0h por - dafg - elr analog pc beep enable: 1 = analog pc beep enabled, 0 = analog pc beep disabled. 8.3.28. afg (nid = 01h): anabtl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7f6h 7f5h 7f4h get ff400h field name bits r/w default reset rsvd3 31 r 0h n/a (hard-coded) reserved. tstriphighstatus 30 r 0h por temp sense high trip point status tstriplowstatus 29 r 0h por temp sense low trip point status tsvolstatus 28:24 r 00h por temp sense volume status for the btl amplifier: 00000b..11111b = range specificity for maxvol field.
idt confidential 70 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo tsmutestatus 23 r 0h por temp sense forced mute status for the btl amplifier. tspwdstatus 22 r 0h por temp sense forced powerdown status for the btl amplifier. rsvd2 21 r 0h n/a (hard-coded) reserved. tsoverridereset 20 rw 0h por override reset for the btl amplifier temperature sensing circuit: set to 1 to re- calculate, set back to 0 to latch the value. tsoverridesel 19 rw 0h por override select for the btl amplifier volume. use maxvol[4:0] and tsoverri- dereset directly to drive analog tstestmode 18 rw 0h por temp sense test mode select, 0=normal operation, 1=sensor will trip at ambi- ent temperature. tsforcepwd 17 rw 0h (ua) 1h (ta) por temp sense force powerdown select 0=btl will not be muted and powered down even if it is still overheating when the volume is 0h 1=btl will be muted and powered down even if it is still overheating when the volume is 0h tsinstantcutmode 16 rw 0h por temp sense instant cut mode 0=two trip points used to smoothly adjust the volume 1=one single trip point used to set volume to wither 0 or max value (ti mode) field name bits r/w default reset
idt confidential 71 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo tswait 15:12 rw 3h por temperature sensing wait time between volume increments 0h = 2ms (polling at 2ms) 1h = 4ms (polling at 4ms) 2h = 8ms (polling at 8ms) 3h = 16ms (polling at 16ms) 4h = 32ms (polling at 16ms) 5h = 64ms (polling at 16ms) 6h = 128ms (polling at 16ms) 7h = 256ms (polling at 16ms) 8h = 512ms (polling at 16ms) 9h = 1.024s (polling at 16ms) ah = 2.048s (polling at 16ms) bh = 4.096s (polling at 16ms) ch = 8.192s (polling at 16ms) dh = 16.384s (polling at 16ms) eh = 32.768s (polling at 16ms) fh = 65.536s (polling at 16ms). tstripsplit 11:10 rw 0h por temp sense split setting, determines how many degrees above the low point the high point is set: 0h = 15 degrees c 1h = 30 degrees c 2h = 45 degrees c 3h = 60 degrees c. tstripshift 9:8 rw 02h por temp sense shift setting, determines where the low point is set: 0h = 110 degrees c 1h = 125 degrees c 2h = 140 degrees c 3h = 155 degrees c rsvd1 7:6 r 0h na reserved monosel 5 rw 0h? por mono select for the btl amplifier, 1=mono, 0=stereo field name bits r/w default reset
idt confidential 72 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo maxvol 4:0 rw 0fh por gain setting for the btl amplifier (tem perature sensing logic will decrement from here): 00000 = -26.25db: 00001 = -19.80db 00010 = -15.80db 00011 = -12.85db 00100 = -10.40db 00101 = -8.27db 00110 = -6.35db 00111 = -4.60db 01000 = -2.90db 01001 = -1.25db 01010 = 0.35db 01011 = 1.98db 01100 = 3.63db 01101 = 5.35db 01110 = 7.19db 01111 = 9.18db 10000 = 9.95db 10001 = 10.75db 10010 = 11.58db 10011 = 12.48db 10100 = 13.43db 10101 = 14.46db 10110 = 15.57db 10111 = 16.79db 11000-11111 = not valid 8.3.29. afg (nid = 01h): anacapless reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7fah 7f9h 7f8h get ff800h field name bits r/w default reset rsvd 31:26 r 00h n/a (hard-coded) reserved. vregscdet 25 r 0h por capless regulator short circuit detect indicator. field name bits r/w default reset
idt confidential 73 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo chargepumpscdet 24 r 0h por capless charge pump short circuit detect indicator. vregsel 23:20 rw 3h por - s&dafg - lr capless regulator output voltage multiply ratio. vregscrstb 19 rw 0h por - s&dafg - lr capless regulator short circuit detect rese t: 0 = short circuit detect disabled, 1 = short circuit detect enabled. vreggndshort 18 rw 0h por - s&dafg - lr ground the capless regulator output. vregpwd 17 rw 0h por - s&dafg - lr capless regulator powerdown. chargepumpscrstb 16 rw 0h por - s&dafg - lr capless charge pump short circuit detect reset: 0 = short circuit detect dis- abled, 1 = short circuit detect enabled. chargepumphiz 15 rw 0h por - s&dafg - lr hi-z the capless charge pump outputs. chargepumppwd 14 rw 0h por - s&dafg - lr capless charge pump powerdown. chargepumpsplydetover- ride 13 rw 1h (ya rev) 0h por - s&dafg - lr capless charge pump supply detect override. chargepumpfreqbypass 12 rw 1h (ya, yc) 0h (yb rev) por - s&dafg - lr capless charge pump frequency reg bypass. field name bits r/w default reset
idt confidential 74 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo chargepumpclkrate 11:8 rw 8h por capless charge pump clock rate: 0000b = 800.0khz (24mhz/30) 0001b = 750.0khz (24mhz/32) 0010b = 706.9khz (24mhz/34) 0011b = 666.7khz (24mhz/36) 0100b = 631.6khz (24mhz/38) 0101b = 600.0khz (24mhz/40) 0110b = 571.4khz (24mhz/42) 0111b = 545.5khz (24mhz/44) 1000b = 800.0khz (24mhz/30) 1001b = 857.1khz (24mhz/28) 1010b = 923.1khz (24mhz/26) 1011b = 1.000mhz (24mhz/24) 1100b = 1.091mhz (24mhz/22) 1101b = 1.200mhz (24mhz/20) 1110b = 1.333mhz (24mhz/18) 1111b = 1.500mhz (24mhz/16) chargepumpclkdiv 7:5 rw 4h por capless charge pump analog clock divider: 001b = no divide 010b = divide by 2, 50% duty cycle 100b = divide by 4, 50% duty cycle 110b = divide by 2, 75% duty cycle 011b = divide by 4, 75% duty cycle 111b = divide by 4, 87.5% duty cycle other values undefined chargepumpclksel 4 rw 0h por capless charge pump clock select: 0 = ring oscillator, 1 = charge pump clock defined by afgcaplesschargepumpclkrate[3:0] field below. padgnd 3 rw 0h por - s&dafg - lr ground the output pad of the capless amplifiers. inputgnd 2 rw 0h por - s&dafg - lr ground the input to the capless output amplifiers. reserved 1 r 0h por reserved antipopbypass 0 rw 0h por anti-pop bypass.. field name bits r/w default reset
idt confidential 75 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.3.31. afg (nid = 01h): auxaudio 8.3.30. afg (nid = 01h): reset reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 7ffh get fff00h field name bits r/w default reset rsvd1 31:8 r 000000h n/a (hard-coded) reserved. execute 7:0 w 00h n/a (hard-coded) function reset. function group reset is executed when the set verb 7ff is written with 8-bit payload of 00h. the codec should issue a response to ac- knowledge receipt of the verb, and then reset the affected function group and all associated widgets to their power-on reset values. some controls such as configuration default controls should not be reset. overlaps response. reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 774h get f7400h field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. mixerpwd 1 rw 0h por aux audio moder mixer powerdown: 0 = mixer enabled during aux audio mode, 1 = mixer forced powered down during aux audio mode. enable 0 rw 1h por aux audio mode select: 0 = aux audio disabled, 1 = aux audio enabled during hda link reset.
idt confidential 76 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.4. porta (nid = 0ah): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 77 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 8.4.1. porta (nid = 0ah): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 78 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo vrefcntrl 15:8 r 17h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 1h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 1h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 8.4.2. porta (nid = 0ah): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset
idt confidential 79 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 03h n/a (hard-coded) number of nid entries in connection list. 8.4.3. porta (nid = 0ah): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) dac2 converter widget (0x22) conl2 23:16 r 1ch n/a (hard-coded) mixeroutvol selector widget (0x1c) conl1 15:8 r 14h n/a (hard-coded) dac1 converter widget (0x14) conl0 7:0 r 13h n/a (hard-coded) dac0 converter widget (0x13) 8.4.4. porta (nid = 0ah): inampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h get b2000h
idt confidential 80 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.4.5. porta (nid = 0ah): inampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h get b0000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.4.6. porta (nid = 0ah): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. index 1:0 rw 0h por - dafg - ulr connection select control index.
idt confidential 81 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.4.7. porta (nid = 0ah): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 8.4.8. porta (nid = 0ah): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h
idt confidential 82 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. hphnen 7 rw 0h por - dafg - ulr headphone amp enable: 1 = enabled, 0 = disabled. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. inen 5 rw 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 4:3 r 0h n/a (hard-coded) reserved. vrefen 2:0 rw 0h por - dafg - ulr vref selection (see vrefcntrl field of pincap parameter for supported selec- tions): 000b= hi-z 001b= 50% 010b= gnd 011b= reserved 100b= 80% 101b= 100% 110b= reserved 111b= reserved 8.4.9. porta (nid = 0ah): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved.
idt confidential 83 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled. rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 8.4.10. porta (nid = 0ah): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 8.4.11. porta (nid = 0ah): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 84 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. rsvd1 0 r 0h n/a (hard-coded) reserved. 8.4.12. porta (nid = 0ah): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 0h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 02h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved field name bits r/w default reset
idt confidential 85 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo device 23:20 rw 2h por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other connectiontype 19:16 rw 1h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other field name bits r/w default reset
idt confidential 86 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo color 15:12 rw 4h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 3h por default assocation. sequence 3:0 rw fh por sequence. 8.5. portb (nid = 0bh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 87 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 88 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 8.5.1. portb (nid = 0bh): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 89 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 0h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 1h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 8.5.2. portb (nid = 0bh): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 03h n/a (hard-coded) number of nid entries in connection list. field name bits r/w default reset
idt confidential 90 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.5.3. portb (nid = 0bh): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) dac2 converter widget (0x22) conl2 23:16 r 1ch n/a (hard-coded) mixeroutvol selector widget (0x1c) conl1 15:8 r 14h n/a (hard-coded) dac1 converter widget (0x14) conl0 7:0 r 13h n/a (hard-coded) dac0 converter widget (0x13) 8.5.4. portb (nid = 0bh): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. index 1:0 rw 0h por - dafg - ulr connection select control index. 8.5.5. portb (nid = 0bh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h
idt confidential 91 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 8.5.6. portb (nid = 0bh): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. hphnen 7 rw 0h por - dafg - ulr headphone amp enable: 1 = enabled, 0 = disabled.
idt confidential 92 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. rsvd1 5:0 rw 00h n/a (hard-coded) reserved. 8.5.7. portb (nid = 0bh): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled. rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 8.5.8. portb (nid = 0bh): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset
idt confidential 93 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 8.5.9. portb (nid = 0bh): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. rsvd1 0 r 0h n/a (hard-coded) reserved. 8.5.10. portb (nid = 0bh): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h
idt confidential 94 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset portconnectivity 31:30 rw 0h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 02h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved device 23:20 rw 2h por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other
idt confidential 95 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo connectiontype 19:16 rw 1h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other color 15:12 rw 1h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 1h por default assocation. sequence 3:0 rw 0h por sequence. field name bits r/w default reset
idt confidential 96 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.6. portc (nid = 0ch): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 97 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 8.6.1. portc (nid = 0ch): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 98 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo vrefcntrl 15:8 r 17h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 1h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 8.6.2. portc (nid = 0ch): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset
idt confidential 99 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 03h n/a (hard-coded) number of nid entries in connection list. 8.6.3. portc (nid = 0ch): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) dac2 converter widget (0x22) conl2 23:16 r 1ch n/a (hard-coded) mixeroutvol selector widget (0x1c) conl1 15:8 r 14h n/a (hard-coded) dac1 converter widget (0x14) conl0 7:0 r 13h n/a (hard-coded) dac0 converter widget (0x13) 8.6.4. portc (nid = 0ch): inampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h get b2000h
idt confidential 100 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.6.5. portc (nid = 0ch): inampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h get b0000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.6.6. portc (nid = 0ch): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. index 1:0 rw 0h por - dafg - ulr connection select control index.
idt confidential 101 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.6.7. portc (nid = 0ch): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 8.6.8. portc (nid = 0ch): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h
idt confidential 102 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:7 r 000000h n/a (hard-coded) reserved. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. inen 5 rw 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 4:3 r 0h n/a (hard-coded) reserved. vrefen 2:0 rw 0h por - dafg - ulr vref selection (see vrefcntrl field of pincap parameter for supported selec- tions): 000b= hi-z 001b= 50% 010b= gnd 011b= reserved 100b= 80% 101b= 100% 110b= reserved 111b= reserved 8.6.9. portc (nid = 0ch): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled.
idt confidential 103 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 8.6.10. portc (nid = 0ch): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 8.6.11. portc (nid = 0ch): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. field name bits r/w default reset
idt confidential 104 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd1 0 r 0h n/a (hard-coded) reserved. 8.6.12. portc (nid = 0ch): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 0h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 02h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved field name bits r/w default reset
idt confidential 105 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo device 23:20 rw ah por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other connectiontype 19:16 rw 1h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other field name bits r/w default reset
idt confidential 106 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo color 15:12 rw 9h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 2h por default assocation. sequence 3:0 rw 0h por sequence. 8.7. portd (nid = 0dh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 107 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 108 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 8.7.1. portd (nid = 0dh): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 109 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo balancedio 6 r 1h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 0h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 0h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 8.7.2. portd (nid = 0dh): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 03h n/a (hard-coded) number of nid entries in connection list. field name bits r/w default reset
idt confidential 110 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.7.3. portd (nid = 0dh): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 1ch n/a (hard-coded) mixeroutvol selector widget (0x1c) conl1 15:8 r 14h n/a (hard-coded) dac1 converter widget (0x14) conl0 7:0 r 13h n/a (hard-coded) dac0 converter widget (0x13) 8.7.4. portd (nid = 0dh): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. index 1:0 rw 0h por - dafg - ulr connection select control index. 8.7.5. portd (nid = 0dh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h
idt confidential 111 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 8.7.6. portd (nid = 0dh): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:7 r 000000h n/a (hard-coded) reserved. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled.
idt confidential 112 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd1 5:0 r 0h n/a (hard-coded) reserved. 8.7.7. portd (nid = 0dh): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. rsvd1 0 r 0h n/a (hard-coded) reserved. 8.7.8. portd (nid = 0dh): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 2h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) field name bits r/w default reset
idt confidential 113 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo location 29:24 rw 10h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved device 23:20 rw 1h por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other field name bits r/w default reset
idt confidential 114 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo connectiontype 19:16 rw 7h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other color 15:12 rw 0h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 1h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 3h por default assocation. sequence 3:0 rw 0h por sequence. field name bits r/w default reset
idt confidential 115 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.8. vendor reserved (nid = 0eh) 8.9. portf (nid = 0fh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no.
idt confidential 116 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 8.9.1. portf (nid = 0fh): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 1h n/a (hard-coded) eapd support: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 117 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 1h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 1h n/a (hard-coded) output support: 1 = yes, 0 = no. hdphdrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 8.9.2. portf (nid = 0fh): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset
idt confidential 118 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 03h n/a (hard-coded) number of nid entries in connection list. 8.9.3. portf (nid = 0fh): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) dac2 converter widget (0x22) conl2 23:16 r 1ch n/a (hard-coded) mixeroutvol selector widget (0x1c) conl1 15:8 r 14h n/a (hard-coded) dac1 converter widget (0x14) conl0 7:0 r 13h n/a (hard-coded) dac0 converter widget (0x13) 8.9.4. portf (nid = 0fh): inampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h get b2000h
idt confidential 119 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.9.5. portf (nid = 0fh): inampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h get b0000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.9.6. portf (nid = 0fh): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:2 r 00000000h n/a (hard-coded) reserved. index 1:0 rw 0h por - dafg - ulr connection select control index.
idt confidential 120 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.9.7. portf (nid = 0fh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 8.9.8. portf (nid = 0fh): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h
idt confidential 121 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:7 r 000000h n/a (hard-coded) reserved. outen 6 rw 0h por - dafg - ulr output enable: 1 = enabled, 0 = disabled. inen 5 rw 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 4:3 r 0h n/a (hard-coded) reserved. vrefen 2:0 rw 0h por - dafg - ulr vref selection (see vrefcntrl field of pincap parameter for supported selec- tions): 000b= hi-z 001b= 50% 010b= gnd 011b= reserved 100b= 80% 101b= 100% 110b= reserved 111b= reserved 8.9.9. portf (nid = 0fh): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled.
idt confidential 122 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 8.9.10. portf (nid = 0fh): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 8.9.11. portf (nid = 0fh): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:2 r 00000000h n/a (hard-coded) reserved. eapd 1 rw 1h por - dafg - ulr eapd control: 1 = set eapd pin to 1 (powered) up if this pin is powered up, 0 = set eapd pin to 0. field name bits r/w default reset
idt confidential 123 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd1 0 r 0h n/a (hard-coded) reserved. 8.9.12. portf (nid = 0fh): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 0h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) location 29:24 rw 01h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved field name bits r/w default reset
idt confidential 124 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo device 23:20 rw 8h por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other connectiontype 19:16 rw 1h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other field name bits r/w default reset
idt confidential 125 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo color 15:12 rw 9h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 0h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 4h por default assocation. sequence 3:0 rw 0h por sequence. 8.10. vendor reserved (nid = 10h) 8.11. dmic0 (nid = 11h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 126 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo type 23:20 r 4h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. digitalstrm 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 1h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 127 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 8.11.1. dmic0 (nid = 11h): pincap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000ch field name bits r/w default reset rsvd2 31:17 r 0000h n/a (hard-coded) reserved. eapdcap 16 r 0h n/a (hard-coded) eapd support: 1 = yes, 0 = no. vrefcntrl 15:8 r 00h n/a (hard-coded) vref support: bit 7 = reserved bit 6 = reserved bit 5 = 100% support (1 = yes, 0 = no) bit 4 = 80% support (1 = yes, 0 = no) bit 3 = reserved bit 2 = gnd support (1 = yes, 0 = no) bit 1 = 50% support (1 = yes, 0 = no) bit 0 = hi-z support (1 = yes, 0 = no) rsvd1 7 r 0h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 128 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo balancedio 6 r 0h n/a (hard-coded) balanced i/o support: 1 = yes, 0 = no. incap 5 r 1h n/a (hard-coded) input support: 1 = yes, 0 = no. outcap 4 r 0h n/a (hard-coded) output support: 1 = yes, 0 = no. hphndrvcap 3 r 0h n/a (hard-coded) headphone amp present: 1 = yes, 0 = no. presdtctcap 2 r 1h n/a (hard-coded) presence detection support: 1 = yes, 0 = no. trigrqd 1 r 0h n/a (hard-coded) trigger required for impedance sense: 1 = yes, 0 = no. impsensecap 0 r 0h n/a (hard-coded) impedance sense support: 1 = yes, 0 = no. 8.11.2. dmic0 (nid = 11h): inampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h get b2000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.11.3. dmic0 (nid = 11h): inampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h field name bits r/w default reset
idt confidential 129 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo get b0000h field name bits r/w default reset rsvd1 31:2 r 00000000h n/a (hard-coded) reserved. gain 1:0 rw 0h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.11.4. dmic0 (nid = 11h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. 8.11.3. dmic0 (nid = 11h): inampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0)
idt confidential 130 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 8.11.5. dmic0 (nid = 11h): pinwcntrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 707h get f0700h field name bits r/w default reset rsvd2 31:6 r 0000000h n/a (hard-coded) reserved. inen 5 rw 0h por - dafg - ulr input enable: 1 = enabled, 0 = disabled. rsvd1 4:0 r 00h n/a (hard-coded) reserved. 8.11.6. dmic0 (nid = 11h): unsolresp reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 708h get f0800h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. en 7 rw 0h por - dafg - ulr unsolicited response enable (also enables wake events for this widget): 1 = enabled, 0 = disabled. field name bits r/w default reset
idt confidential 131 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd1 6 r 0h n/a (hard-coded) reserved. tag 5:0 rw 00h por - dafg - ulr software programmable field returned in top six bits (31:26) of every unsolicit- ed response generated by this node. 8.11.7. dmic0 (nid = 11h): chsense reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 709h get f0900h field name bits r/w default reset presdtct 31 r 0h por presence detection indicator: 1 = presence detected; 0 = presence not detect- ed. rsvd 30:0 r 00000000h n/a (hard-coded) reserved. 8.11.8. dmic0 (nid = 11h): configdefault reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 71fh 71eh 71dh 71ch get f1f00h / f1e00h / f1d00h / f1c00h field name bits r/w default reset portconnectivity 31:30 rw 2h por port connectivity: 0h = port complex is connected to a jack 1h = no physical connection for port 2h = fixed function device is attached 3h = both jack and internal device attached (info in all other fields refers to in- tegrated device, any presence detection refers to jack) field name bits r/w default reset
idt confidential 132 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo location 29:24 rw 10h por location bits [5..4]: 0h = external on primary chassis 1h = internal 2h = separate chassis 3h = other bits [3..0]: 0h = n/a 1h = rear 2h = front 3h = left 4h = right 5h = top 6h = bottom 7h-9h = special ah-fh = reserved device 23:20 rw ah por default device: 0h = line out 1h = speaker 2h = hp out 3h = cd 4h = spdif out 5h = digital other out 6h = modem line side 7h = modem handset side 8h = line in 9h = aux ah = mic in bh = telephony ch = spdif in dh = digital other in eh = reserved fh = other field name bits r/w default reset
idt confidential 133 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo connectiontype 19:16 rw 3h por connection type: 0h = unknown 1h = 1/8" stereo/mono 2h = 1/4" stereo/mono 3h = atapi internal 4h = rca 5h = optical 6h = other digital 7h = other analog 8h = multichannel analog (din) 9h = xlr/professional ah = rj-11 (modem) bh = combination ch-eh = reserved fh = other color 15:12 rw 0h por color: 0h = unknown 1h = black 2h = grey 3h = blue 4h = green 5h = red 6h = orange 7h = yellow 8h = purple 9h = pink ah-dh = reserved eh = white fh = other misc 11:8 rw 1h por miscellaneous: bits [3..1] = reserved bit 0 = jack detect override association 7:4 rw 4h por default assocation. sequence 3:0 rw eh por sequence. field name bits r/w default reset
idt confidential 134 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.12. reserved (nid = 12h) 8.13. dac0 (nid = 13h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 0h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r dh n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 1h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no.
idt confidential 135 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 8.13.1. dac0 (nid = 13h): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. strmtype 15 r 0h n/a (hard-coded) stream type: 1 = non-pcm, 0 = pcm. field name bits r/w default reset
idt confidential 136 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz. smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 8.13.2. dac0 (nid = 13h): procstate (ra revision only) reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 703h get f0300h field name bits r/w default reset
idt confidential 137 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:2 r 000000h n/a (hard-coded) reserved. dachpfbyp 1:0 rw 1h por - dafg - ulr processing state: 00b= bypass the dac hpf (""off""), 01b-11b= dac hpf is enabled (""on"" or ""benign"").". 8.13.3. dac0 (nid = 13h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 8.13.4. dac0 (nid = 13h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved.
idt confidential 138 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 8.13.5. dac0 (nid = 13h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 3h por - dafg - lr current power state setting for this widget. field name bits r/w default reset
idt confidential 139 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.13.6. dac0 (nid = 13h): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). 8.13.7. dac0 (nid = 13h): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:3 r 00000000h n/a (hard-coded) reserved. swapen 2 rw 0h por - dafg - ulr swap enable: 1 = l/r swap enabled, 0 = l/r swap disabled. rsvd1 1:0 r 0h n/a (hard-coded) reserved.
idt confidential 140 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.13.8. dac0 (nid = 13h): procindex (ra revision only) reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 782h get f8200h field name bits r/w default reset rsvd 31:3 r 000000h n/a (hard-coded) reserved. coeffindex 2:0 rw 2h por - dafg - ulr processing coeff selection. 0 = -3db response at 100hz 1 = -3db response at 200hz 2 = -3db response at 300hz 3 = -3db response at 400hz 4 = -3db response at 500hz 5 = -3db response at 750hz 6 = -3db response at 1000hz 7 = -3db response at 2000hz 8.14. dac1 (nid = 14h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved.
idt confidential 141 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo type 23:20 r 0h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r dh n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 1h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 142 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 8.14.1. dac1 (nid = 14h): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. strmtype 15 r 0h n/a (hard-coded) stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz. smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved field name bits r/w default reset
idt confidential 143 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 8.14.2. dac1 (nid = 14h): procstate (ra revision only) reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 703h get f0300h field name bits r/w default reset rsvd 31:2 r 000000h n/a (hard-coded) reserved. dachpfbyp 1:0 rw 1h por - dafg - ulr processing state: 00b= bypass the dac hpf (""off""), 01b-11b= dac hpf is enabled (""on"" or ""benign"").". field name bits r/w default reset
idt confidential 144 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.14.3. dac1 (nid = 14h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 8.14.4. dac1 (nid = 14h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. gain 6:0 rw 7fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 8.14.5. dac1 (nid = 14h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h
idt confidential 145 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 3h por - dafg - lr current power state setting for this widget. 8.14.6. dac1 (nid = 14h): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h 8.14.5. dac1 (nid = 14h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0)
idt confidential 146 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). 8.14.7. dac1 (nid = 14h): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:3 r 00000000h n/a (hard-coded) reserved. swapen 2 rw 0h por - dafg - ulr swap enable: 1 = l/r swap enabled, 0 = l/r swap disabled. rsvd1 1:0 r 0h n/a (hard-coded) reserved. 8.14.8. dac1 (nid = 14h): procindex (ra revision only) reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 782h get f8200h
idt confidential 147 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:3 r 000000h n/a (hard-coded) reserved. coeffindex 2:0 rw 2h por - dafg - ulr processing coeff selection. 0 = -3db response at 100hz 1 = -3db response at 200hz 2 = -3db response at 300hz 3 = -3db response at 400hz 4 = -3db response at 500hz 5 = -3db response at 750hz 6 = -3db response at 1000hz 7 = -3db response at 2000hz 8.15. dac2 (nid = 22h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r fh n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget.
idt confidential 148 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 0h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 0h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 0h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). field name bits r/w default reset
idt confidential 149 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.15.1. dac2 (nid = 22h): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. strmtype 15 r 0h n/a (hard-coded) stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 r 0h n/a (hard-coded) sample base rate: 1 = 44.1khz, 0 = 48khz. smplratemultp 13:11 r 0h n/a (hard-coded) sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved smplratediv 10:8 r 0h n/a (hard-coded) sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved.
idt confidential 150 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo bitspersmpl 6:4 r 0h n/a (hard-coded) bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 r 0h n/a (hard-coded) total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 8.15.2. dac2 (nid = 22h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. mute 7 r 0h n/a (hard-coded) amp mute: 1 = muted, 0 = not muted. gain 6:0 r 00h n/a (hard-coded) amp gain step number (see outampcap parameter pertaining to this widget). 8.15.3. dac2 (nid = 22h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset
idt confidential 151 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. mute 7 r 0h n/a (hard-coded) amp mute: 1 = muted, 0 = not muted. gain 6:0 r 00h n/a (hard-coded) amp gain step number (see outampcap parameter pertaining to this widget). 8.15.4. dac2 (nid = 22h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 0h n/a (hard-coded) indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h n/a (hard-coded) error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 0h n/a (hard-coded) actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved.
idt confidential 152 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo set 1:0 r 0h n/a (hard-coded) current power state setting for this widget. 8.15.5. dac2 (nid = 22h): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 r 0h n/a (hard-coded) stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 r 0h n/a (hard-coded) channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). 8.15.6. dac2 (nid = 22h): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:3 r 00000000h n/a (hard-coded) reserved. swapen 2 r 0h n/a (hard-coded) swap enable: 1 = l/r swap enabled, 0 = l/r swap disabled. rsvd1 1:0 r 0h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 153 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.16. adc0 (nid = 15h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 1h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r dh n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 154 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo procwidget 6 r 1h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 8.16.1. adc0 (nid = 15h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. field name bits r/w default reset
idt confidential 155 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.16.2. adc0 (nid = 15h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 17h n/a (hard-coded) adc0mux selector widget (0x18) 8.16.3. adc0 (nid = 15h): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. strmtype 15 r 0h n/a (hard-coded) stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz.
idt confidential 156 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 8.16.4. adc0 (nid = 15h): procstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 703h get f0300h field name bits r/w default reset
idt confidential 157 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. hpfocdis 7 rw 0h por - dafg - ulr hpf offset calculation disable. 1 = calculation disabled; 0 = calculation en- abled. rsvd1 6:2 r 00h n/a (hard-coded) reserved. adchpfbyp 1:0 rw 1h por - dafg - ulr processing state: 00b= bypass the adc hpf ("off"), 01b-11b= adc hpf is en- abled ("on" or "benign"). 8.16.5. adc0 (nid = 15h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved.
idt confidential 158 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 3h por - dafg - lr current power state setting for this widget. 8.16.6. adc0 (nid = 15h): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). 8.17. adc1 (nid = 16h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 159 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo type 23:20 r 1h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r dh n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 1h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 160 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo ampparovrd 3 r 0h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 8.17.1. adc1 (nid = 16h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. 8.17.2. adc1 (nid = 16h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset
idt confidential 161 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 18h n/a (hard-coded) adc1mux widget (0x18) 8.17.3. adc1 (nid = 16h): cnvtr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 2h get a0000h field name bits r/w default reset rsvd2 31:16 r 0000h n/a (hard-coded) reserved. strmtype 15 r 0h n/a (hard-coded) stream type: 1 = non-pcm, 0 = pcm. frmtsmplrate 14 rw 0h por - dafg - ulr sample base rate: 1 = 44.1khz, 0 = 48khz. smplratemultp 13:11 rw 0h por - dafg - ulr sample base rate multiple: 000b= x1 (48khz/44.1khz or less) 001b= x2 (96khz/88.2khz/32khz) 010b= x3 (144khz) 011b= x4 (192khz/176.4khz) 100b-111b reserved
idt confidential 162 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo smplratediv 10:8 rw 0h por - dafg - ulr sample base rate divider: 000b= divide by 1 (48khz/44.1khz) 001b= divide by 2 (24khz/20.05khz) 010b= divide by 3 (16khz/32khz) 011b= divide by 4 (11.025khz) 100b= divide by 5 (9.6khz) 101b= divide by 6 (8khz) 110b= divide by 7 111b= divide by 8 (6khz) rsvd1 7 r 0h n/a (hard-coded) reserved. bitspersmpl 6:4 rw 3h por - dafg - ulr bits per sample: 000b= 8 bits 001b= 16 bits 010b= 20 bits 011b= 24 bits 100b= 32 bits 101b-111b= reserved nmbrchan 3:0 rw 1h por - dafg - ulr total number of channels in the stream assigned to this converter: 0000b-1111b= 1-16 channels. 8.17.4. adc1 (nid = 16h): procstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 703h get f0300h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. hpfocdis 7 rw 0h por - dafg - ulr hpf offset calculation disable. 1 = calculation disabled; 0 = calculation en- abled. field name bits r/w default reset
idt confidential 163 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd1 6:2 r 00h n/a (hard-coded) reserved. adchpfbyp 1:0 rw 1h por - dafg - ulr processing state: 00b= bypass the adc hpf ("off"), 01b-11b= adc hpf is en- abled ("on" or "benign"). 8.17.5. adc1 (nid = 16h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 3h por - dafg - lr current power state setting for this widget. field name bits r/w default reset
idt confidential 164 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.17.6. adc1 (nid = 16h): cnvtrid reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 706h get f0600h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. strm 7:4 rw 0h por - s&dafg - lr - ps stream id: 0h = converter "off", 1h-fh = valid id's. ch 3:0 rw 0h por - s&dafg - lr - ps channel assignment ("ch" and "ch+1" assi gned as a pair, for a stereo convert- er). 8.18. adc0mux (nid = 17h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 3h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined
idt confidential 165 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 1h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. digitalstrm 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparamovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). field name bits r/w default reset
idt confidential 166 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.18.1. adc0mux (nid = 17h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 07h n/a (hard-coded) number of nid entries in connection list. 8.18.2. adc0mux (nid = 17h): conlstentry4 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0204h field name bits r/w default reset conl7 31:24 r 00h n/a (hard-coded) unused list entry. conl6 23:16 r 0ah n/a (hard-coded) port a pin widget (0x0a) in tb silicon unused list entry in ra silicon. conl5 15:8 r 12h n/a (hard-coded) reserved conl4 7:0 r 11h n/a (hard-coded) dmic0 pin widget (0x11) in tb silicon port a pin widget (0x0a) in ra silicon
idt confidential 167 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.18.3. adc0mux (nid = 17h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 1bh n/a (hard-coded) mixer summing widget (0x1b) in tb silicon dmic0 pin widget (0x11) in ra silicon conl2 23:16 r 0fh n/a (hard-coded) port f pin widget (0x0f) in tb silicon mixer summing widget (0x1b) in ra silicon conl1 15:8 r 0eh n/a (hard-coded) port e pin widget (0x0e) (port e not available) in tb silicon port f pin widget (0x0f) in ra silicon conl0 7:0 r 0ch n/a (hard-coded) port c pin widget (0x0c) in tb and ra silicon 8.18.4. adc0mux (nid = 17h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 05h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps.
idt confidential 168 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 0fh n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 00h n/a (hard-coded) indicates which step is 0db 8.18.5. adc0mux (nid = 17h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:4 r 0h n/a (hard-coded) reserved. gain 3:0 rw 0h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 8.18.6. adc0mux (nid = 17h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset
idt confidential 169 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:4 r 0h n/a (hard-coded) reserved. gain 3:0 rw 0h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 8.18.7. adc0mux (nid = 17h): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. index 2:0 rw 0h por - dafg - ulr connection select control index. 8.18.8. adc0mux (nid = 17h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved.
idt confidential 170 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 8.18.9. adc0mux (nid = 17h): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h field name bits r/w default reset rsvd2 31:3 r 00000000h n/a (hard-coded) reserved. swapen 2 rw 0h por - dafg - ulr swap enable: 1 = l/r swap enabled, 0 = l/r swap disabled. rsvd1 1:0 r 0h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 171 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.19. adc1mux (nid = 18h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 3h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 1h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. digitalstrm 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no.
idt confidential 172 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparamovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 8.19.1. adc1mux (nid = 18h): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 07h n/a (hard-coded) number of nid entries in connection list. field name bits r/w default reset
idt confidential 173 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.19.2. adc1mux (nid = 18h): conlstentry4 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0204h field name bits r/w default reset conl7 31:24 r 00h n/a (hard-coded) unused list entry. conl6 23:16 r 0ah n/a (hard-coded) port a pin widget (0x0a) in tb silicon unused list entry in ra silicon. conl5 15:8 r 12h n/a (hard-coded) reserved conl4 7:0 r 11h n/a (hard-coded) dmic0 pin widget (0x11) in tb silicon port a pin widget (0x0a) in ra silicon 8.19.3. adc1mux (nid = 18h): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 1bh n/a (hard-coded) mixer summing widget (0x1b) in tb silicon dmic0 pin widget (0x11) in ra silicon conl2 23:16 r 0fh n/a (hard-coded) port f pin widget (0x0f) in tb silicon mixer summing widget (0x1b) in ra silicon
idt confidential 174 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo conl1 15:8 r 0eh n/a (hard-coded) port e pin widget (0x0e) (port e not available) in tb silicon port f pin widget (0x0f) in ra silicon conl0 7:0 r 0ch n/a (hard-coded) port c pin widget (0x0c) in tb and ra silicon 8.19.4. adc1mux (nid = 18h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 05h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 0fh n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 00h n/a (hard-coded) indicates which step is 0db field name bits r/w default reset
idt confidential 175 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.19.5. adc1mux (nid = 18h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:4 r 0h n/a (hard-coded) reserved. gain 3:0 rw 0h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 8.19.6. adc1mux (nid = 18h): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:4 r 0h n/a (hard-coded) reserved. gain 3:0 rw 0h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget).
idt confidential 176 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.19.7. adc1mux (nid = 18h): conselectctrl reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 701h get f0100h field name bits r/w default reset rsvd 31:3 r 00000000h n/a (hard-coded) reserved. index 2:0 rw 0h por - dafg - ulr connection select control index. 8.19.8. adc1mux (nid = 18h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved.
idt confidential 177 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.20. reserved (nid = 19h) 8.21. reserved (nid = 1ah) act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 8.19.9. adc1mux (nid = 18h): eapdbtllr reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ch get f0c00h 8.22. mixer (nid = 1bh): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 178 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo type 23:20 r 2h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no. formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. field name bits r/w default reset
idt confidential 179 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo ampparovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 0h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 1h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 8.22.1. mixer (nid = 1bh): inampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000dh field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 05h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 1fh n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. field name bits r/w default reset
idt confidential 180 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo offset 6:0 r 17h n/a (hard-coded) indicates which step is 0db 8.22.2. mixer (nid = 1bh): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 06h n/a (hard-coded) number of nid entries in connection list. 8.22.3. mixer (nid = 1bh): conlstentry4 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0204h field name bits r/w default reset conl7 31:24 r 00h n/a (hard-coded) unused list entry. conl6 23:16 r 00h n/a (hard-coded) unused list entry. field name bits r/w default reset
idt confidential 181 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo conl5 15:8 r 0ah n/a (hard-coded) port a pin widget (0x0a). uses inampleft5/inampright5 controls tb silicon unused list entry in ra silicon conl4 7:0 r 14h n/a (hard-coded) dac1 converter widget (0x14). uses inampleft4/inampright4 controls in tb silicon port a pin widget (0x0a). uses inampleft4/inampright4 controls ra silicon 8.22.4. mixer (nid = 1bh): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset conl3 31:24 r 13h n/a (hard-coded) dac0 converter widget (0x13). uses inampleft3/inampright3 controls in tb silicon dac1 converter widget (0x14). uses inampleft3/inampright3 controls in ra silicon conl2 23:16 r 0fh n/a (hard-coded) port f pin widget (0x0f). uses inampleft2/inampright2 controls in tb silicon dac0 converter widget (0x13). uses inampleft2/inampright2 controls in ra silicon conl1 15:8 r 0eh n/a (hard-coded) port e pin widget (0x0e). uses inampleft1/inampright1 controls. (port e not supported). tb silicon port f pin widget (0x0f). uses inampleft1/inampright1 controls in ra silicon conl0 7:0 r 0ch n/a (hard-coded) port c pin widget (0x0c). uses inampleft0/inampright0 controls in tb and ra silicon 8.22.5. mixer (nid = 1bh): inampleft0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 360h field name bits r/w default reset
idt confidential 182 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo get b2000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.22.6. mixer (nid = 1bh): inampright0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 350h get b0000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.22.5. mixer (nid = 1bh): inampleft0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0)
idt confidential 183 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.22.7. mixer (nid = 1bh): inampleft1 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 361h get b2001h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.22.8. mixer (nid = 1bh): inampright1 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 351h get b0001h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget).
idt confidential 184 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.22.9. mixer (nid = 1bh): inampleft2 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 362h get b2002h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.22.10. mixer (nid = 1bh): inampright2 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 352h get b0002h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget).
idt confidential 185 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.22.11. mixer (nid = 1bh): inampleft3 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 363h get b2003h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.22.12. mixer (nid = 1bh): inampright3 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 353h get b0003h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget).
idt confidential 186 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.22.13. mixer (nid = 1bh): inampleft4 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 364h get b2004h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.22.14. mixer (nid = 1bh): inampright4 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 354h get b0004h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget).
idt confidential 187 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.22.15. mixer (nid = 1bh): inampleft5 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 365h get b2005h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget). 8.22.16. mixer (nid = 1bh): inampright5 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 355h get b0005h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 17h por - dafg - ulr amp gain step number (see inampcap param eter pertaining to this widget).
idt confidential 188 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.22.17. mixer (nid = 1bh): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 8.23. mixeroutvol (nid = 1ch): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h
idt confidential 189 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 3h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined delay 19:16 r 0h n/a (hard-coded) number of sample delays through widget. rsvd1 15:12 r 0h n/a (hard-coded) reserved. swapcap 11 r 0h n/a (hard-coded) left/right swap support: 1 = yes, 0 = no. pwrcntrl 10 r 1h n/a (hard-coded) power state support: 1 = yes, 0 = no. dig 9 r 0h n/a (hard-coded) digital stream support: 1 = yes (digital), 0 = no (analog). connlist 8 r 1h n/a (hard-coded) connection list present: 1 = yes, 0 = no. unsolcap 7 r 0h n/a (hard-coded) unsolicited response support: 1 = yes, 0 = no. procwidget 6 r 0h n/a (hard-coded) processing state support: 1 = yes, 0 = no. stripe 5 r 0h n/a (hard-coded) striping support: 1 = yes, 0 = no.
idt confidential 190 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo formatovrd 4 r 0h n/a (hard-coded) stream format override: 1 = yes, 0 = no. ampparovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no. inampprsnt 1 r 0h n/a (hard-coded) input amp present: 1 = yes, 0 = no. stereo 0 r 1h n/a (hard-coded) stereo stream support: 1 = yes (stereo), 0 = no (mono). 8.23.1. mixeroutvol (nid = 1ch): conlst reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f000eh field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. lform 7 r 0h n/a (hard-coded) connection list format: 1 = long-form (15-bi t) nid entries, 0 = short-form (7-bit) nid entries. conl 6:0 r 01h n/a (hard-coded) number of nid entries in connection list. 8.23.2. mixeroutvol (nid = 1ch): conlstentry0 reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0200h field name bits r/w default reset
idt confidential 191 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset conl3 31:24 r 00h n/a (hard-coded) unused list entry. conl2 23:16 r 00h n/a (hard-coded) unused list entry. conl1 15:8 r 00h n/a (hard-coded) unused list entry. conl0 7:0 r 1bh n/a (hard-coded) mixer summing widget (0x1b) 8.23.3. mixeroutvol (nid = 1ch): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 05h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 1fh n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved.
idt confidential 192 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo offset 6:0 r 1fh n/a (hard-coded) indicates which step is 0db 8.23.4. mixeroutvol (nid = 1ch): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 1fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 8.23.5. mixeroutvol (nid = 1ch): outampright reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 390h get b8000h field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 1h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. field name bits r/w default reset
idt confidential 193 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd1 6:5 r 0h n/a (hard-coded) reserved. gain 4:0 rw 1fh por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 8.23.6. mixeroutvol (nid = 1ch): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget. rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. field name bits r/w default reset
idt confidential 194 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 8.24. reserved (nid = 1dh) 8.25. reserved (nid = 1eh) 8.26. reserved (nid = 1fh) 8.27. reserved (nid = 19h) 8.28. reserved (nid = 20h) 8.29. digbeep (nid = 21h): wcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0009h field name bits r/w default reset rsvd3 31:24 r 00h n/a (hard-coded) reserved. type 23:20 r 7h n/a (hard-coded) widget type: 0h = out converter 1h = in converter 2h = summing (mixer) 3h = selector (mux) 4h = pin complex 5h = power 6h = volume knob 7h = beep generator 8h-eh = reserved fh = vendor defined rsvd2 19:4 r 0h n/a (hard-coded) reserved. ampparovrd 3 r 1h n/a (hard-coded) amplifier capabilities override: 1 = yes, no. outampprsnt 2 r 1h n/a (hard-coded) output amp present: 1 = yes, 0 = no.
idt confidential 195 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd1 1:0 r 0h n/a (hard-coded) reserved. 8.29.1. digbeep (nid = 21h): outampcap reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set get f0012h field name bits r/w default reset mute 31 r 1h n/a (hard-coded) mute support: 1 = yes, 0 = no. rsvd3 30:23 r 00h n/a (hard-coded) reserved. stepsize 22:16 r 17h n/a (hard-coded) size of each step in the gain range: 0 to 127 = .25db to 32db, in .25db steps. rsvd2 15 r 0h n/a (hard-coded) reserved. numsteps 14:8 r 03h n/a (hard-coded) number of gains steps (number of possible settings - 1). rsvd1 7 r 0h n/a (hard-coded) reserved. offset 6:0 r 03h n/a (hard-coded) indicates which step is 0db 8.29.2. digbeep (nid = 21h): outampleft reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 3a0h get ba000h field name bits r/w default reset
idt confidential 196 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo field name bits r/w default reset rsvd2 31:8 r 000000h n/a (hard-coded) reserved. mute 7 rw 0h por - dafg - ulr amp mute: 1 = muted, 0 = not muted. rsvd1 6:2 r 00h n/a (hard-coded) reserved. gain 1:0 rw 1h por - dafg - ulr amp gain step number (see outampcap parameter pertaining to this widget). 8.29.3. digbeep (nid = 21h): pwrstate reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 705h get f0500h field name bits r/w default reset rsvd4 31:11 r 000000h n/a (hard-coded) reserved. settingsreset 10 r 1h por - dafg - ulr indicates if any persistent settings in this widget have been reset. cleared by pwrstate 'get', or a 'set' to any verb in this widget. rsvd3 9 r 0h n/a (hard-coded) reserved. error 8 r 0h por - dafg - ulr error indicator: 1 = cannot enter requested power state, 0 = no problem with requested power state. rsvd2 7:6 r 0h n/a (hard-coded) reserved. act 5:4 r 3h por - dafg - lr actual power state of this widget.
idt confidential 197 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo rsvd1 3:2 r 0h n/a (hard-coded) reserved. set 1:0 rw 0h por - dafg - lr current power state setting for this widget. 8.29.4. digbeep (nid = 21h): gen reg byte 4 (bits 31:24) byte 3 (bits 23:16) byte 2 (bits 15:8) byte 1 (bits 7:0) set 70ah get f0a00h field name bits r/w default reset rsvd 31:8 r 000000h n/a (hard-coded) reserved. divider 7:0 rw 00h por - dafg - lr enable internal pc-beep generation. divi der == 00h disables internal pc beep generation and enables normal operation of the codec. divider != 00h gener- ates the beep tone on all pin complexes that are currently configured as out- puts. the hd audio spec states that the beep tone frequency = (48khz hd audio sync rate) / (4*divider), producing tones from 47 hz to 12 khz (logarith- mic scale). field name bits r/w default reset
idt confidential 198 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 9. pinout 9.1. pin assignment figure 11. pin assignment 40-qfn dvdd_lv sdata_out bitclk sdata_in dvdd* sync reset# pcbeep 1 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 13 14 21 22 23 24 25 26 27 28 29 30 38 37 36 35 34 33 32 31 40 39 sense_a sense_b portc_l portc_r portf_l portf_r vrefout_a vrefout_c vreffilt cap2 cap- v- avdd1 avss2 portb_r portb_l avss2 porta_r porta_l vreg(+2.5v) avdd2 eapd pvdd dmic_clk/gpio 1 dmic_0/gpio 2 cap+ portd_+r portd_-r portd_-l portd_+l pvss pvdd
idt confidential 199 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 9.2. pin table pin name pin function i/o internal pull-up/pull-down pin location dvdd_core 1.5v digital core regulator filter cap o(digital) none 1 dmic_clk/gpio1 digital mic clock output/gpio1 i/o(digital) 60k pull-down 2 dmic0/gpio2 digital mic 0 input/gpio2 i/o(digital) 60k pull-down 3 sdata_out hd audio serial data output from controller i/o(digital) none 4 bitclk hd audio bit clock i(digital) none 5 sdata_in hd audio serial data input to controller o(digital) none 6 dvdd digital vdd= 3.3v i(digital) none 7 sync hd audio frame sync i(digital) none 8 reset# hd audio reset i(digital) none 9 pcbeep pc beep i(analog) none 10 sense_a jack insertion detection ports a, b,c i(analog) none 11 sense_b jack insertio n detection ports e,f i(analog) none 12 portf_l port f left i/o(analog) none 13 portf_r port f right i/o(analog) none 14 portc_l port c left i/o(analog) none 15 portc_r port c right i/o(analog) none 16 vreffilt analog virtual ground o(analog) none 17 cap2 reference filter cap o(analog) none 18 vrefout-a reference voltage out drive (for mic bias) o(analog) none 19 vrefout-c reference voltage out drive (for mic bias) o(analog) none 20 avdd1 analog vdd=5.0v or 3.3v i(analog) none 21 porta_l (hp0) port a output left i/o(analog) none 22 porta_r (hp0) port a output right i/o(analog) none 23 avss analog ground i(analog) none 24 portb_l (hp1) port b output left i/o(analog) none 25 portb_r (hp1) port b output right i/o(analog) none 26 avss analog ground i(analog) none 27 v- negative analog supply o(analog) none 28 cap- charge pump cap - o(analog) none 29 cap+ charge pump cap + o(analog) none 30 vreg linear regulator output (2.5v) filter cap o(analog) none 31 avdd2 analog supply for vreg i(analog) none 32 pvdd analog supply for class-d amp i(analog) none 33 portd_+l btl amp left + o(analog) none 34 portd_-l btl amp left - o(analog) none 35 pvss analog ground i(analog) none 36 table 24. pinout list
idt confidential 200 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 9.3. package outline and package dimensions package dimensions are kept curr ent with jedec publication no. 95 figure 12. 40qfn package diagram portd_-r btl amp right - o(analog) none 37 portd_+r btl amp right + o(analog) none 38 pvdd analog supply for class-d amp i(analog) none 39 eapd eapd i/o (open drain digital) 60k pull-up 40 pin name pin function i/o internal pull-up/pull-down pin location table 24. pinout list pod in bottom view 5.000.10 31 40 11 1 10 20 30 21 dap size 3.8 x 3.8 co.35 3.500.10 3.500.10 0.400.10 5.000.10 0.35 ref. 0.40 ref. 0.20 +0.05 -0.03 pod in side view 0.850.05
idt confidential 201 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 9.4. standard reflow profile data note: these devices can be hand soldered at 360 o c for 3 to 5 seconds. from: ipc / jedec j-std-020c ?moisture/reflow se nsitivity classification for nonhermetic solid state surface mount devices? (www.jedec.org/download). figure 13. solder reflow profile profile feature pb free assembly average ramp-up rate (ts max - tp) 3 o c / second max preheat: temperature min (ts min ) temperature max (ts max ) time (ts min - ts max ) 150 o c 200 o c 60 - 180 seconds time maintained above: temperature (t l ) time (t l ) 217 o c 60 - 150 seconds peak / classification temperature (tp) see ?package classification reflow temperatures? time within 5 o c of actual peak temper ature (tp) 20 - 40 seconds ramp-down rate 6 o c / second max time 25 o c to peak temperature 8 minutes max note: all temperatures refer to topside of the package, measured on the package body surface. table 25. standard reflow profile
idt confidential 256 v 0.995 01/11 ?2009 integrated device technology, inc. 92hd88 92hd88 single chip pc aud io system, codec+mono speaker amplifier+capless hp+ldo 9. disclaimer while the information presented he rein has been checke d for both accuracy an d reliability, manufac- turer assumes no responsibility for ei ther its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal co mmercial applications. any other applications, such as those requiring extended temper ature range, high reliability, or other extraord inary environmental requirements, are not recommended without additi onal processing by manufacturer. manufacturer reserves the right to change any circuitry or spec ifications without notice. manufacturer does not authorize or warrant any product for use in life support devices or critic al medical instruments.
idt confidential 203 v 0.995 01/11 ?2009 integrated device technology, inc. 92HD87 92HD87 single chip pc aud io system, codec+stereo spe aker amplifier+capless hp+ldo 11. document revision history revision date description of change 0.93 april 2010 initial release 0.94 july 2010 added aux mode description section 0.95 october 2010 portc as input only for tb silicon revision 0.99 october 2010 sa revision, port c is input and output. btl/sd _mode default changed. hi gh pass filter feature added (description and widgets to control dac0/1 procstate and procindex ), updated datasheet formatting to new style. ecr15b references changed to hda015-b. removed preliminary. 0.99 november 2010 additional sa revision changes. adc0mux, adc1mux and mixer widgets connection lists differ from tb silicon. values for both revisions listed for each con# item. 0.995 january 2011 updated sa revision comments for ra revisions.
92hd88 single chip pc aud io system, codec+mono speaker amplifier+capless hp+ldo 6024 silver creek valley road san jose, california 95138 disclaimer integrated device technology, inc. (idt) and its subs idiaries reserve the right to mo dify the products and/or specif ications de- scribed herein at any time and at idt?s sole discretion. all in formation in this document, including descriptions of product fe atures and perfor- mance, is subject to change without notice. performance specifications and the operati ng parameters of the described products a re determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the information co ntained herein is provided without repres entation or warranty of any kind, whether express or implied, including, but not limited to, t he suitability of idt?s products for any particular purpose, an implied warranty of merc hantability, or non-infringement of the intellectual property r ights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other tra demarks and service marks used he rein, in- cluding protected names, logos and desi gns, are the property of idt or their respective third party owners.

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